| Very long instruction word (VLIW) architecture offers an opportunity for superior multiprocessor digital signal professor implementations. By eschewing the hardware resource management provided in superscalar and superpipelined processor implementations, a VLIW processor has more available hardware resources for computations. The disadvantages of the VLIW approach are that object code is no longer compatible across multiple generations of processors and that the compilation technology to support a VLIW processor is more complicated than that required by traditional processor architectures.;This dissertation describes a VLIW architecture for digital signal processing. The described architecture has multiple functional units, including a residue number system convolution processor. The convolution processor is based upon the Athena sensor arithmetic processor, a 1.2 billion operation per second SIMD convolution processor, which is also described. To solve the difficulties associated with software development for a VLIW digital signal processing microprocessor, a new high-level language based upon the C programming language is described. Implementations of several key digital signal processing algorithms are analyzed with respect to opportunities for instruction-level and block-level parallelism, and their resource requirements in the context of a VLIW digital signal processing environment. |
