A Low-power RISV-V Processor For Post-quantum Cryptography

Information security is an important part of the Internet of Things(Io T).Encrypted data transmission and identity authentication between devices all need to be protected by cryptography algorithms.With the rapid development of quantum computer and efficient quantum algorithms,traditional public key cryptography algorithms are no longer secure.Therefore,post-quantum cryptography(PQC)algorithms which can resist the attack of quantum computer are proposed.However,PQC algorithms are difficult to deploy and apply to resource-limited Io T end devices due to its large computation volume and complex computation form.Recently,researchers all over the world have proposed a variety of hardware accelerators for PQC algorithms.Among these designs,the scheme of Application Specific Instruction set Processors(ASIP)has the characteristics of strong universality and low cost,which is very suitable for the Io T scenario.However,the existing ASIP designs still have three problems to be solved:”low reuse of specific circuits for acceleration”,”large limit of load and store” and ”complex dataflow”.In order to solve these problems,aiming at low power consumption and low cost,this study combined the hardware design with the characteristics of PQC algorithm to fully improve the utilization rate of hardware while accelerating the algorithm execution.Three hardware design points and four software acceleration methods are proposed.The combination of the operator fusion method in software and the recombination of the computing components in hardware is used to solve the problem of ”low reuse of specific circuits for acceleration”.The adjustment of data flow and parallel computing method in software are combined with the parallel dataflow in hardware to solve the problem of ”complex dataflow”.The parallel execution of load&and computing instructions in software is combined with Superscalar execution in hardware to solve the problem of ”large limit of load and store”.The proposed processor has been functionally verified to correctly run Kyber and Dilithium,two PQC algorithms for public key encryption and digital signature respectively,and has up to10 times the speed improvement compared to 32-bit processors.Compared with recent works,the proposed processor has the smallest area and the lowest power consumption,and the Figure of Merit is the best.The proposed ASIP scheme for PQC algorithms is very suitable for resource-limited Io T end devices.