Research On Key Operation Architecture Design Technology Of Reconfigurable Lattice-Based Post-Quantum Cryptography Algorithm

Lattice-based post-quantum public key cryptography algorithm has become a trusted cryptographic algorithm among international standards organizations and national security departments.This is due to its provable difficulty in solving lattice problems and the efficiency of practical application.Currently,based on the collection standards of the National Institute of Standards and Technology(NIST),the core operations in different candidate algorithms involve polynomial multiplication that consumes a significant amount of time.Therefore,how to quickly implement polynomial multiplication in different algorithms in hardware is of great research value and practical significance.This paper focuses on the research of high-speed reconfigurable polynomial multiplication architecture design technology for the core operation of different latticebased post-quantum cryptography algorithms,namely polynomial multiplication.The main objectives of the work are as follows:Aiming at the current situation that the polynomial multiplication parameters are different and the implementation architecture is not unified in lattice-based public key cryptography algorithms,this paper proposes a reconfigurable computing architecture based on Pt NTT algorithm.Firstly,the influence of polynomial parameters(number of items,modulus and modulus polynomial)on reconfigurable architecture is integrated by analyzing the characteristics of polynomial multiplication.Secondly,a 4×4 serial-parallel convertible computing unit is designed for different terms and modular polynomials,which can meet the scalable design of k-based theory transformation with different bit widths.Specifically,a reconfigurable unit that can realize 16-bit modular multiplication and 32-bit multiplication is designed for different modules.At the same time,an interconnection control mechanism combining Crossbar and fixed connection is proposed based on the above operation network characteristics,which provides a more flexible interconnection structure to meet more possible algorithms in the future.Aiming at the problem that the hardware implementation of polynomial multiplication consumes a lot of time,a 2n-order unit root preprocessing number theory transform operation architecture optimized by Karatsuba algorithm is proposed on the basis of reconfigurable architecture.The algorithm uses the parallel processing of the small bit width number theory transform and the low complexity calculation form to reduce the operation time.This paper determines the KNTT implementation algorithm based on the minimum computational complexity,and designs the overall operation architecture and unified butterfly operation unit matching the algorithm.On this basis,by the evaluation system of performance per unit area,the 16-way parallel architecture scheme is obtained combined with the influence of storage granularity and pipeline depth on the selection of parallelism.Aiming at the problem of complex address translation caused by the interaction of large amounts of data in the process of high-speed reconfigurable computing,this paper proposes a nonpreset multi-Bank storage data allocation mechanism that satisfies the k-based number theory transformation.Based on the constraint that the coefficients in the classical NTT algorithm have a flip-preset transform,the paper proposes a non-preset data transformation method that satisfies kbased 2n/n unit root NTT algorithms and simplifies the coefficient address conversion.In the process of data requirement analysis,a multi-Bank storage structure that satisfies k-based NTT is designed by constructing a distribution mechanism based on coefficient address generation,Bank division,and address correspondence logic.The experimental results show that this paper supports the polynomial multiplication in Kyber,Saber,Dilithium and NTRU algorithms.Compared with the other reconfigurable architectures,the architecture implements polynomial multiplication among the four algorithms using a unified framework,and the performance is improved by 1.91 times.Compared with the other single algorithm design,the performance is increased by 6% to 15.81 times.In 65 nm CMOS technology,a set of polynomial multiplication operations with 256 terms and 3329 moduli can be completed in 0.449 μs,which consumes 214 clocks.The highest operating frequency can reach 476 MHz,and the area time product is 206.50(kGE·μs).