Research On Reconfigurable Hardware Implementation Of Number Theoretic Transform For Lattice-Based Cryptography

Post quantum cryptography can resist the brute force attack of quantum computer and meet the requirements of future communication security,so it becomes the next generation of public key cryptography.In the post quantum cryptography,lattice cryptography has received the most attention and research because of its small public key,fast speed and good diversity.The security of lattice-based cryptography depends on the security parameters,and the performance depends on the core operators,namely polynomial generation operator and polynomial multiplication operator.In the implementation of polynomial multiplication operator,number theoretic transformation is widely used because of its simple algorithm and easy hardware implementation.This paper studies and designs a reconfigurable number theoretic transformation hardware unit for lattice-based cryptography,which can realize high performance and multiple security parameters of polynomial multiplication operation,and meet the operation requirements of lattice-based cryptography in different scenarios.Firstly,based on the algorithm of single-lane number theoritical transformation and hardware implementation,this paper proposes a multi-lanes number theoretic transformation algorithm to simplify the address generation operation in number theoretic transformation.Secondly,two kinds of modular adder / subtractor and three kinds of modular multipliers with different algorithms are studied.By analyzing the synthesised results of modular multipliers with 16 parameters,the performance and resource consumption of modular multipliers are obtained.Then,a reconfigurable modular multiplier based on RAM is designed to update the value in RAM through reconfiguration operation,so as to realize modular multiplication operation under different modulars.Based on this,a reconfigurable butterfly operation unit is designed.Then,according to the multi-lanes number theoretic transformation algorithm,a multi-channel butterfly operation architecture is designed.On this basis,a reconfigurable multi-channel number theoretic transformation unit is further designed,which can realize the polynomial multiplication operation under four polynomial dimensions and 16 modulars.Finally,the functional simulation of RTL level project is carried out on vivado 2018,and the results show that the designed reconfigurable number theoretic transformation unit can correctly perform polynomial multiplication,which reduces the theoretical operation time by75% compared with the classical implementation.According to the resource report of synthesis and layout and wiring,the design occupies 3884 LUTs,1444 Slices,24 BRAMs and 16 DPSs,and the maximum speed is 232.3 MHz.At the same time,the prototype verification is completed on the Artix-7 FPGA platform.In summary,the reconfigurable number theoretic transform unit designed in this paper supports 4 kinds of polynomial dimensions and 16 kinds of modular parameter reconstruction operations without changing the resource consumption and performance.It has the best comprehensive performance in the FPGA implementation of polynomial multiplication of correlated lattice-based cryptography,and has significant application value.