| This article takes positioning and navigation as the application requirement,and based on IP core multiplexing technology,aims to achieve the transplantation of processor software and hardware and the reconstruction of baseband signal processing systems.The main task of this project is to complete the prototype design of the global positioning and navigation system(GPS)L1 band(center frequency 1575.42 MHz)baseband system on chip(So C)chip based on the Cortex-M3 soft core,study the key baseband technologies,implement the processor’s control and scheduling of baseband IP by writing software programs,and test and verify the baseband IP with simulated satellite data in different modes.The original baseband system in the laboratory uses ARM926EJ＿S The hardware architecture of the S-type processor(CPU)chip is a baseband system on chip built using the Advanced Microprocessor Bus Architecture(AMBA)bus protocol.It internally integrates memory modules,baseband processing modules,external interfaces,and other related circuits.Prototype verification is performed on a field programmable gate array(FPGA)development board for circuit mapping,and the final realization is the board cascade tuning of CPU+FPGA.Aiming at the problem of high power consumption and high cost of GPS baseband signal processing So C built on ARM926EJ-S type hard core solidified processor chip,an open source Cortex-M3 soft core processor based on ARM Design Strat plan is proposed to build a GPS baseband So C system by multiplexing GPS baseband IP.Integrate the soft core processor and baseband signal processing into one,and complete the design and collaborative implementation of baseband processing So C software and hardware modules according to the needs of software design and hardware implementation.In terms of hardware,the system selects Cortex-M3 soft core processor and bus as the core for baseband signal processing design,designs a system bus matrix and several cores that comply with the protocol,constructs the overall structure of the advanced high-performance bus(AHB)and peripheral bus(APB),and completes the system integration of baseband and other related IPs.The system mainly includes: clock management module,on-chip read-only memory(ROM),decoder,multiplexer Bus matrix,random access memory(RAM)module,bridge,universal asynchronous transceiver(UART)interface,universal input output(IO)interface,etc.Realize the expansion of So C system functions.The software part completes the initialization and startup of the system through assembly and C language,and compiles specific test signals for the satellite navigation baseband circuit to achieve flexible configuration of the software for baseband IP.It completes the testing of baseband IP in different modes,and compares and analyzes the consistency of the waveform when the processor outputs control signals to the baseband module before and after transplantation.The results show that the data transmission is correct and meets the bus timing requirements.Finally,a software and hardware simulation platform was built to verify the internal functional modules and migration test files of So C under different test modes.Board level testing was conducted through the FPGA simulation platform,achieving software and hardware collaborative simulation verification,ensuring the correctness and completeness of system functions.The system achieves the expected functions and meets the requirements for low power consumption and micro integration of devices. |
