Deployment Optimization Of Convolutional Neural Network Based On Memristor Arrays

Memristor is one of the most studied devices in the field of neuromorphic computing.Memristor is smaller in size and of lower power in work than the CMOS device.It is usually integrated into a crossbar array structure,which can perform matrix multiplication with lower complexity.And the integration of storage and calculation is expected to solve the "Memory Wall" problem of the traditional von Neumann computing system.From this perspective,the memristor is suitable for the development of wearable or portable edge smart terminals.However,the memristive device is still in development,and memristor array resources are limited.So designing special networks in small size or proposing corresponding network compression deployment strategies are of practical significance for guiding the construction of physical circuits and exploring properties of memristor integrating storage and computing for memristive arrays.This thesis explores the deployment and compression of convolutional neural network based on memristive arrays to recognize handwritten digits.Besides,a hybrid training fault-tolerant optimization framework for the actual memristor array is designed.This work can provide theoretical and practical guidance for the actual promotion and application of memristors.The contents are as follows:(1)Aiming at solving the problem that mapping one weight by dual memristors requires more memristive resources,while mapping one weight by single memristor may lead to a low accuracy in the previous network compression method,an improved particle swarm algorithm with resource constraints is proposed as an optimal strategy for convolutional neural network deployment in a mixed way by mapping weights using both dual memristors and single memristor.In order to get a better accuracy,the parameters which mapped on the same word line of memristor array are used as a fine granularity search unit.To ensure the reasonableness of solutions,the network performance and the number of memristors are both used in the step of fitness calculation.And in order to speed up the search speed,a mixing ratio constraint is added before the above step.(2)Aiming at solving the problem that the convolutional network model after mixed mapping still needs many memristor hardware resources,a hybrid compression method based on fine-grained structure is proposed.The "block" structured pruning method is used to compress the network in rows and columns at the same time,which can reduce the consumption of hardware resources and take little effect to the accuracy.The combination of mixed mapping deployment and fine-grained pruning can get a better balance between network accuracy and required resources.This thesis also provides the data path of the compressed network which mapped on the crossbar arrays.(3)Aiming at solving the problem that the memristor defect may affect the accuracy of the network model and the on-chip discrete network is difficult to train,a hybrid training fault-tolerant optimization method based on target sparsity is proposed.To reduce the impact of defects on the accuracy of the network,a matching algorithm combined greedy and bipartite graph is proposed.The method of target sparse,through the sparse network,allows some memristor with fault can also be used in the correct mapping.Using software and hardware at the same time to train the network model can use the fault tolerance of network to decrease the effect caused by some memristors with defect.Besides,this framework can also solve the problem of discrete networks and reduce the complexity of circuit design.The thesis studies the memristor model and the weights mapping way in memristor arrays,and improves the mapping method.To further explore the effectiveness of the hybrid mapping deployment optimization method,a hybrid compression based on fine-grained structure is designed.Considering the various problems that may be encountered in the deployment of the network model on crossbar arrays,a hybrid training fault-tolerant optimization method based on target sparsity is proposed.Through the demonstration of relevant theoretical and analysis of experimental simulation,the correctness and feasibility of these methods in this thesis are verified,and it provides a guidance for the application of memristors in actual circuits.