Design And Verification Of Fast Charging Chip Digital Circuit Based On USB PD Protocol

In the world of rapid and universal development of high technology,more and more people begin to enjoy the convenience and happiness brought by electronic devices.People put forward higher requirements on the battery life of mobile phones,and the traditional charging method has exposed the disadvantages of too slow charging speed,so the fast charging protocol came into being.It is in this situation that the USB PD protocol comes into being,which supports the fast charging of a wide range of Type-C interfaces,as well as the"high voltage small current"and"low voltage large current"charging modes.Compared with other protocols,its maximum power up to100W,and special charging devices is not needed.Therefore,it is of great practical value to carry out research on them.This paper is mainly divided into four parts,the introduction of the system architecture of USB PD protocol;Design of fast charging protocol chip digital circuit system;Simulation and verification of circuit design;The function of the circuit system is tested.The details are as follows:1.Detailed analysis of the working mechanism of the USB PD protocol,the basic structure of the system is divided into Physical Layer,Protocol,Policy Engine,and Device Policy Manager to explain the role of each part,and how they work together.2.Specific design scheme of four parts of the protocol circuit:(1)Divide the physical layer into three parts:4b/5B encoding and decoding,CRC-32 codes'calculation and verification,BMC encoding and decoding.The codec circuit is implemented by summarizing the logical relationship of 4b/5b.Parallel input of one-byte wide data can theoretically implement CRC-32 code calculation for infinite data,and improve the circuit to avoid errors.BMC decoding is implemented by state machine,and a sixth-order FIR filter is added,which improves the anti-jamming ability of decoding circuit,and has excellent performance in area and power consumption.(2)The protocol layer is divided into two parts,sending and receiving.The message is organized and deconstructed in the format specified by the protocol according to the instructions of the policy engine layer through the design and implementation of sending and receiving state machines.(3)The policy engine layer mainly needs to ensure that the system sends and receives messages in accordance with the fixed message sequence specified in the PD protocol,which is implemented by a three-segment state machine.Decide what to do next based on the state;Respond to commands from device management and control protocol layer to send new content.(4)In the design,the Device Policy Manager works together through the state machine module,I2C slave module,interrupt generation and processing module to achieve the function of interaction between SINK and upper computer.3.Validate the design by simulation.In the built verification environment,VCS simulation is performed on the circuits of each module at each level.The physical layer4b/5b codec,BMC codec circuit,CRC calculation and check code circuit stability are very high.The state machines of the three different layers can work normally,and several levels collaborate to complete the communication with the built test end on the CC line.4.A prototype validation environment is built using the devices such as FPGA,Printed Circuit Boards of peripheral circuit,STM32 Micro Control Unit(MCU)and PD protocol analyzer.The function of the circuit system is tested.The result shows that the message sending and receiving between Receiver terminal and power supply can be achieved through the upper machine-read or write register,and the switch of power supply voltage in fast charging mode can be completed successfully.Finally,Design Compile is carried out on the tool of Synopsys,the area and power consumption are estimated,the net list is generated.The processing forms the layout of the entire chip,using HHGRACE 0.35?m BCD process,the area of the chip is 2470*1700?m~2.