Power Delivery Protocol Chip Decoding System With Hign Robustness

With the increasing charging power of intelligent mobile devices,the fast charging protocol chip to ensure the security of devices in the process of high-power charging has attracted extensive attention of scholars at home and abroad.USB Power Delivery(PD)3.0 protocol based on type-C interface and both supporting high voltage with small current and low voltage with large current has gradually become the mainstream fast charging protocol.Because the type-C interface supports multiple audio and video transmission protocols at the same time,and the number of cables in the package is limited,only one Configuration Channel(CC)can be used for USB PD 3.0 protocol communication,and USB PD 3.0 is a half duplex communication protocol.As a result,the decoding system of PD protocol chip has no clock cable,no feedback loop.And both ends of the line is easy to occupy the line at same time.On the other hand,hundreds of watts of power transmission line and 20 Gbps of high-speed communication line in cable package make the parasitic capacitance and inductance in CC line channel larger,which leads to DC imbalance of communication signal and data loss and dislocation.In this paper,four strategies are proposed to solve the above problems,and through the implementation,simulation and testing of the proposed strategy.The feasibility and effectiveness are proved,so as to improve the robustness of USB PD 3.0 protocol decoding system.The main contents of this paper are as follows:1.Four strategies to enhance the robustness of USB PD 3.0 protocol chip are proposed.(1)The strategy of 4B/5B coding and adding Cyclic Redundancy Check(CRC)bits in data packetBy using 4B/5B coding to increase the frequency of high level in the signal and shorten the single time duration,the AC component in the signal is improved and the balance of DC is enhanced.In addition,the effective part of the packet is substituted into the CRC-32 algorithm,and then the calculated check code is attached to the packet and sent together.In this way,when the packet is successfully received,the receiver compares the extracted CRC check code with the CRC check code calculated again,so as to judge whether there is code loss or error in the process of data transmission.(2)The strategy of training virtual clock by Biphase Mark Coding(BMC)preambleTaking advantage of the fact that BMC coded signal is similar to clock signal in waveform changing of every UI(Unit Interval),the strategy of adding 64 bits 0 and 1cyclic sequence after BMC coding as preamble in the data packet is adopted.The data receiver could firstly train the virtual clock by oversampling the preamble,and then receives the data packet.Therefore,the strategy could ensure the reliability of data packet decoding and solve the problem of no clock cable.(3)The strategy of adding good CRC message based on CRC result as feedback signal.Firstly,the good CRC message defined by ourself is added to the previous message list.When the receiver obtains a packet and the CRC result is correct,it replies the good CRC message to the sender within 1ms,so as to feedback that the packet has been successfully received.Furthermore,the unique identifier(message ID)of the data packet is added to the good CRC message,which can be used to interpret the feedback of which data packet the good CRC message is for.So the good CRC message has the instantaneity and pertinence of feedback signal,and solves the problem of no feedback loop.(4)The strategy of building AMS by sacrificing the flexibility of a single messageBy defining multiple messages that can complete a certain function into a set of fixed message sequence as an Atomic Message Sequence(AMS).The maximum time interval between messages in a message group is 10 ms,which could ensure the communication order of both sides by sacrificing the flexibility of a single message,so as to avoid the two ends of communication seizing CC line.Therefore,the strategy could solve the contradiction of half duplex communication through a single line.2.Four strategies to enhance robustness are used to design and simulate the PD protocol decoding system based on TSMC 0.18?m process.(1)Design and simulation of 4B/5B coding module and CRC check moduleIn the design of 4B/5B coding module,the principle diagram of the encoding and decoding circuit between 4B code and 5B code is obtained by the method of column truth table,and the circuit diagram is compiled by Verilog Compiled Simulation(VCS).The simulation results show that: the module can complete 4B to 5B and 5B to 4B decoding at 19.2MHz;Furthermore,through the test of 100000 groups of random codes,it shows that 4B/5B coding module can ignore the redundant codes in 5B code,the decoding error rate is less than 0.05 ‰,and the switching frequency of high and low level is increased by 72.4%;In the design of CRC check module,firstly,the the module operation in CRC-32 algorithm is transformed into XOR operation which is easy to be realized by the circuit,and then the circuit is realized by hardware description language.Finally,the circuit is simulated by VCS.The results show that the module can complete8-bit CRC-32 algorithm in one clock cycle at the frequency of 30 k Hz.In addition,the case of code loss and dislocation caused by noise interference is simulated by the valid data and CRC check code in the data packet are randomly changed,and the simulation results are in good agreement with the experimental results in the process of transmission.After 18.2 million tests,the recognition rate of error code is 99.788%,which shows high reliability.(2)Design and simulation of the BMC encoding and decoding circuit.First,an Finite Impulse Response(FIR)filter module is added to the traditional decoding circuit.Then,the counter is separated from the traditional decoding module,and a state machine is added in the decoding module,so that the BMC signal with single cycle change less than ± 25% can be successfully decoded,and the BMC signal with multiple continuous cycle changes can be successfully decoded.Finally,the circuit is simulated by VCS.The results show that when the frequency deviation in the same packet is less than 30%,the virtual clock trained by oversampling the preamble of 64 bit BMC code can replace the real clock.(3)Design and simulation of the Rx and Tx modules that generating and receiving good CRC messagesBy using the method of checking the data packet while receiving,the time of generating good CRC message is advanced,so that the Tx module can complete the sending of good CRC message within 1ms.The Rx module takes the message receiving completion flag as the condition for the counter to add 1,so as to generate the message ID used for the good CRC messages.The circuit is simulated by VCS,and the results show that the module can send good CRC message within 100 ?s at the frequency of30 k Hz,and the message ID value is correct.In addition,by simulating the noise interference,if the packet and CRC check code do not match,the module will not reply with good CRC messages,and will not update the message ID value,so as to prove that the good CRC message has the characteristics of instant and targeted feedback signal.(4)Design and simulate of the strategy engine layer of AMS mechanism.Firstly,the principle of AMS mechanism is expressed by circuit diagram,and then the working process of the circuit is expressed by state transition diagram.Finally,the circuit is simulated by VCS.The results show that the module can control AMS messages to be sent in a fixed order at the frequency of 30 k Hz.In addition,the PD protocol chip can send a Hard Reset message and return to the initial state,when the receiver model interrupts the communication sequence,which proves that AMS mechanism can ensure the orderly communication between the two parties,avoid the communication parties seizing the CC line.3.Four strategies to enhance the robustness of PD protocol chip decoding system are tested.(1)The strategy of improving the anti-interference ability of signal by 4B/5B coding and adding CRC check bit is tested.Through the eye diagram of 3000 waveforms,it is proved that the change of eye height from 0.15 UI to 0.9UI is less than 5%,which indicates that the signal encoded by4B/5B has no potential collapse,so it can be judged that the signal DC is balanced.In addition,the jitter of the rising edge and falling edge of the eye diagram is less than0.05 UI,so the probability of bit error is low,and the signal quality can be judged to be high.On the other hand,the protocol tester sends some missing or misplaced data packets to the PD protocol chip,and the PD protocol chip does not make any reply within 1ms,which proves that the PD protocol chip can identify the missing or misplaced data in the transmission process,and has strong anti-interference ability.(2)The strategy of training virtual clock by BMC coded preamble is testedBy observing the data packet sequence on CC line with oscilloscope,PD protocol chip can make correct response to the received message,which shows that the interpretation of data packet based on virtual clock is correct.On the other hand,the oscillograph of the data packet in the real scene on the CC line is measured by the oscilloscope.It can be seen that the maximum frequency difference of different parts of the data packet after noise interference is 5.6%,which is 30% lower than the design threshold.It is proved that the virtual clock trained by the preamble of BMC code can complete the data packet reception,so as to solve the problem of no clock line.(3)The strategy of replacing feedback signal with good CRC message is testedThe waveform of Source Cap message and good CRC message captured by oscilloscope can prove that PD protocol chip replies to the good CRC message within100?s after receiving the message,which has the instantaneity of feedback signal and does not affect the communication of the next message.In addition,the fast charge tester parses some good CRC messages returned PD protocol chip.According to the incremental value of message ID,it can be proved that the good CRC message has the pertinence of feedback signal.(4)The AMS mechanism to solve the contradiction between single line and half duplex is tested.In the process of communication between PD protocol chip and power adapter,the fast charge tester detects that the message sequence of AMS does not collide.In addition,through the analysis of the message content,it can be seen that the PD protocol chip requests another party to supply power at 12 V,15V and 20 V respectively.From the voltage on the Vbus line change to the 12.1V,15.064 V,20.1V,it shows that the communication is successful,and the power supply terminal provides the corresponding voltage.It is proved that the contradiction between single line and half duplex can be solved successfully by AMS mechanism.