Design Of Low Power And High Precision ΣΔADC Based On Audio Application

Among many ADC architectures,ΣΔ ADC is widely used in audio applications due to its simple circuit structure,low sensitivity to device matching and process deviation,and ability to achieve high-precision conversion.In this thesis,a 20 KHz low-power and high-precision ΣΔADC is designed for audio applications.This thesis focuses on the research and design of the ΣΔ modulator,the core part of the ADC:1.On the system design level,to achieve high-precision conversion,the modulator adopts a full-differential discrete-time 4-order single-bit quantization CIFB structure,and the OSR is determined to be 128.To improve the maximum stable input range,the feed-forward branch from the modulator input to the integrator input is introduced to cancel the signal components in the output of the first three integrators,thus avoiding the overload of the quantizer caused by the excessive total signal power in the loop.2.On the circuit design level,the switched capacitor integrator of the core circuit module is optimized,and the structure of sharing sampling capacitors between the feedforward branch and feedback branch is creatively proposed,which saves nearly 1/3 of switches and capacitors,reduces dynamic power consumption,and saves chip area.The input signal and the feed-forward branches share the sampling switch to reduce nonlinearity,which adopts the bootstrap switch.In addition,a boosted clock driver is designed to control the NMOS switch to sample the feedback signal with a high level of 2VDD,which greatly reduces the nonlinearity introduced by the feedback branch.The circuit-level design is completed in the 180 nm CMOS process,and the layout area is 440μm × 550μm.The post-simulation results show that when the frequency of the input signal is 6.25 KHz,the maximum stable input amplitude is-4d BFS,the peak SNDR is 102 d B,ENOB is 16.7 and the power consumption is only3.46 m W at 1.8V supply voltage,all of which meet the target specifications.At last,the mathematical model of the digital decimation filter is designed in Matlab.