Research And Application Of MOSFET Model Based On Surface Potential

In recent years,smart and convenient wireless communication technology has been developed rapidly,and the Internet of Everything has brought a variety of smart electronic devices into our lives.RF front-end integrated circuits have become the key to research in academia and industry,and the design of integrated circuits is often limited by semiconductor technology.In order to meet the needs of the latest communication technology and integrated circuit design,the physical size of advanced semiconductor process devices needs to be continuously reduced,thereby increasing the cut-off frequency of active devices.Among various semiconductor processes,at the same process node,the cost of III-V compound process semiconductors is relatively high,and it is difficult to be widely used in civilian products.While silicon-based MOSFETs have many advantages such as mature process,low cost and power consumption,high reliability and integration.It has become the first choice for most radio frequency chips.And the research on the process device model has received more and more attention.Accurate device models play an irreplaceable guiding role in circuit design and semiconductor process iteration and development.Based on the CMOS 65 nm process,a series of studies on transistor models have been done in this paper.Firstly,this article clarifies the necessity and importance of model research by studying the development history and research status of silicon-based MOSFET device models,and briefly introduces the basic physical structure and working principle of MOSFET and the physical base surface potential model.Next,in order to obtain accurate transistor test data,based on the theory of multiphysics port coupling,the complete embedded test structure was accurately modeled firstly,and then the test data was deembedded using the de-embedding method combining testing and model calculation in this paper.On this basis,parasitic/coupling effects and multi-finger distribution effects are considered in the transistor model,and a small-signal equivalent circuit model of the transistor under full bias conditions is established,and the accuracy of the model is verified.Then,based on the small signal model of fully biased conditions,a symmetric nonlinear capacitance model that satisfies charge conservation and high-order conduction is established based on the gate charge empirical model in this paper.It has been verified that the model can accurately describe the intrinsic capacitance characteristics of the transistor.In addition,combining the many characteristics and advantages of the physical base model,through the study of the surface potential theory and the channel charge distribution,the surface potential implicit function equation is derived firstly,and then the nonlinear bias-dependent channel length modulation is applied in the drain-source current model in this paper.At the same time,based on the study and research on the distribution characteristics of the transistor channel carriers,the Gaussian distribution function is proposed to describe the non-uniform distribution of carriers,and an improved drain-source current model is further proposed in this paper.After actual taped-out and tested,the proposed nonlinear drain-source current model based on surface potential can reduce the root mean square error of the model by an order of magnitude in the all bias conditions in this paper.Finally,the improved nonlinear capacitance model and current model are applied to the transistor power simulation.The verification results show that the model in this paper not only has fewer empirical parameters,but also characterizes the output power,power added efficiency and gain characteristics of the transistor more accurately.