Design And Logic Gate Circuit Optimization Of Multi-ring Tunneling Field Effect Transistor

As the size of MOSFET approaching its physical limit,the short channel effect,increased leakage current and power consumption caused by size reduction become the main reason for limiting the development of integrated circuits.In addition,MOSFET can not achieve a sub-threshold swing(SS)below 60m V/dec at room temperature because it is limited by the Boltzmann of thermodynamic transport.For solving the above problems,researchers have proposed various new devices,such as NCFET and TFET.Tunneling field effect transistor(TFET)can break the limit of MOSFET SS at room temperature because of its band-to-band tunneling(BTBT)mechanism.Beyond that,the manufacturing process of TFETs is compatible with the CMOS technology,which can meet the requirements of higher integration and lower working voltage.Due to the low ON-state current and serious bipolar effect of traditional TFET devices,the application of it in practical circuits is hindered.Researchers have made a profound study,and TFET has become a research hotspot in the field of advanced devices.The research content of this paper mainly starts from the optimization of device structure,studies its improvement of electrical characteristics.The specific works are as follows:Firstly,a multi-ring gate tunneling field effect transistor(MR-TFET)structure is proposed.The ring-shaped source region embedded in channel region,so that both longitudinal and transverse tunneling occur,and the density of carriers increases.As shown in the TCAD simulation results,the ON-state current of the device is significantly improved from 1.75×10⁵ to 5.63×10⁵ by increasing the area of tunneling junction.Otherwise,the switching ratio of MR-TFET is improved by 3.1 times.Secondly,the effects of different structure parameters,doping methods and doping concentrations on the device are analyzed and discussed from two aspects of DC and AC characteristics,and the idea of device optimization design is put forward.The TCAD simulation results show that 1)The ON-state current increased by 4.8 times when the thickness of channel decreases from 9nm to 5nm.2)When the thickness of source is reduced to 5nm,the ON-state current can be enhanced by 18.5%.3)The SS can be reduced to 37 m V/dec by using 2nm Hf O₂ as gate dielectric.4)When Gaussian doping is used in the source and drain region,the switching ratio of the MR-TFET is the largest,which can reach 9.02×10⁶.Finally,based on the optimization of DC and AC characteristics of the MR-TFET,the effects of some parameters on the propagation delay and power consumption of the inverter circuit are analyzed.The simulation results show that 1)The inverter circuit based on the device with the source size of 5nm wide and 30nm high can gain the lowest propagation delay under different V_DD.When V_DD=0.2V,it is reduced by 38.1%and 26.2%compared with the other two structures respectively.2)When Lun is 20 nm,the propagation delay of the inverter circuit is reduced by 41.2%compared with the inverter based on Lun=0 nm device.3)In contrast to the inverter circuit based on the device with T_ch=9 nm,the performance of that with T_ch=5 nm is the best,which is reduced by33.1%.In summary,the above research contents and results can provide an effective reference for the technology research and industrialization of the TFET.