High-speed Serial Link Modeling And PAM4 Floating-tap DFE Design

In recent years,with rapid development of the Internet communications,Ethernet has entered the era of high-speed transmission.PAM4 signal is widely used because its half bandwidth compared to NRZ,which makes it more adaptable to the high-speed serial links.However,as the frequency-related loss becomes more serious and the factors affecting signal integrity increase,the design of high-speed serial links faces many challenges.It is necessary to optimize the design of each module of the link as a whole to improve the transmission performance.This thesis first studies two channel modeling methods of the high-speed serial link:COM(Channel Operating Margin)-based and machine-learning-based channel modeling of high-speed serial links.Firstly,based on the definition of COM,by revising the reference model of the NRZ link,a COM link model for PAM4 is designed.And the thesis compares the modeling results of COM-based and BER-based eye diagrams on PAM4 signals to prove the correctness of the established PAM4 COM model.Then,this thesis uses machine learning methods,takes the characteristic variables that affect the channel characteristics as the model input.Based on the random forest regression algorithm(RFR),through model training and testing,a channel model represented by S-parameters is obtained.In order to improve the accuracy of the model,a modeling method combining coarse and fine is proposed,which achieves a good compromise between efficiency and accuracy.This thesis also studies the design of a PAM4 decision feedback equalizer(DFE)with 1 fixed tap+2floating taps based on 55nm CMOS process.The circuit includes key modules such as CTLE,three-level slicer,D flip-flop,multiplexer and multiplier-adder,among which the selection of floating tap data is realized by the multiplexer.This thesis completes the layout design and post-simulation of the design circuit.The layout area including the pads is 0.411mm~2.The simulation results show that after equalization,the eye diagram of the 40Gb/s PAM4 signal passing through the channel with a loss of 12d B at 10GHz is significantly improved,and the horizontal opening of the eye diagram reaches 0.68UI,which meets the design requirements.Under the trend of rapid growth of data transmission rate,the PAM4-based high-speed serial link modeling and floating-tap DFE design studied in this thesis have certain application value for assisting channel design engineers in channel design and improving the quality of transmission signals.