Design Of Rail-to-rail Operational Amplifier With High Bandwidth,Low Noise And Low Power Consumption

Rail-to-rail operational amplifier(RTR OP),which is close to the input and output signal range of the power supply voltage,has been widely used in basic analog circuits in many fields such as communication and digital-to-analog conversion.For the accuracy and speed of operational amplifiers,obtaining sufficient gain and bandwidth under low power constraints has become a significant and urgent challenge in Rt R OP design.In the traditional operational amplifier,the increase of gain and bandwidth is usually at the cost of large static power consumption,and the interaction between low power consumption and high response greatly increases the difficulty of operational amplifier circuit design.The design of low power rail-to-rail high bandwidth high precision operational amplifier has academic significance and practical value.The key and difficulty of rail-to-rail amplifier design lies in constant transconductance control of input stage.Under the condition of making full use of the input current,the transconductance curve should be obtained as gently as possible,which is beneficial to the frequency compensation and high bandwidth design of the op-amp.Based on two input stage constant-transconductance structures of constant current control and quadruple tail current control,two rail-to-rail operational amplifiers are designed in this paper.Based on TSMC 0.35μm CMOS standard process and 3.3V power supply voltage,the circuit parameters were designed and verified by Cadence simulation platform.Based on the existing laboratory conditions,the performances of the two circuit schemes are simply tested and evaluated.The test results show that both the two circuits can realize the input and output rail-to-rail functions.In the constant current control scheme,the total static current is less than220μA.The positive and negative slew rates are 4.4V/μs and 7.4V/μs,respectively.The DC gain is92 d B～97d B.The unit gain bandwidth is 9.6MHz and the phase margin is 47.5° under the condition of 47 p F load capacitance.In the quadruple tail current control scheme,the positive and negative slew rates are 3.8V/μs and 9.4V/μs,respectively.The DC gain is 90 d B～94d B.The unit gain bandwidth is9.3MHz and the phase margin is 49.3° under the condition of 47 p F load capacitance.The chips basically meet the expected test requirements.Compared with the simulation results,some parameters are degraded to different degrees.The reasons for the degradation are analyzed and a feasible improvement scheme is given.