Design Of Constant Transconductance CMOS Rail-to-rail Operational Amplifier

Integrated circuits continue to lower the supply voltage, with the rapid development of portable electronic devices, which will force the input and output signal swing of operational amplifier (here in after referred to as the op-amp) greatly reduced, and which can seriously affect the performance of op-amp, even not to work. In order to improve the signal-to-noise ratio of the op-amp, the input and output signal range of op-amp usually requires to reach the entire supply voltage, Rail-to-Rail.Based on the understanding of the domestic and international research on Rail-to-Rail operational amplifiers, the paper studies how to accomplish the input signal scope and the output signal scope to achieve the entire amplitude of the low voltage op-amp and how to accomplish input stage with stable transconductance and output stage with high voltage efficiency, in the view of standard CMOS technology. It also studies the structure and the principles of electric circuits, including how achieves Rail-to-Rail input/output stage and the constant transconductance. On the basis of the related technical achievement, improved design proposal has been put forward and confirmed feasible implementation.A Rail-to-Rail operational amplifier is designed at3.3V single power supply. The input stage which satisfies the demand of Rail-to-Rail common mode input range with significant constant transconductance characteristics is a complementary differential pair controlled by three-times current mirror; the op-amp employs a feed-forward biased class-AB output stage controlled by the floating current source, meeting the requirements of the Rail-to-Rail output voltage dynamic range with precise control of the output transistor current. The folded-cascode structure is used as intermediate amplifier stage, which can realize the function of summing circuit and the steady static output current and increase the loop gain.Based on0.18um CMOS technology, Cadence Spectra tool is used for the simulation. With the supply voltage3.3V, the load resistance5KΩ, and the load capacitance10pF, the simulation results indicate that the operational amplifier has achieved open loop DC gain of120dB, unit gain bandwidth of6.55MHz, phase margin of66.4degree, power dissipation of0.36mW, and the transconductance variation over the common-mode input range of only about2.45%. For its simple and compact structure, this operational amplifier cell is suitable for low voltage and low power consumption application.