Design Of A High Gain Constant-g_m Low Offset Rail To Rail Amplifier

Operational amplifier is one of the most important and basic analog building blocks, andhas been widely applied in measuring instruments, A/D converter, and filter etc. With thedevelopment of semiconductor technology, the feature size of the CMOS has beencontinuously decreased, the power supply voltage has been reduced a lot, and the voltagerange of the input common mode and the output swing has been substantially decreased aswell. In order to maintain the signal to noise ratio, the amplifier requires a rail to rail input andoutput dynamic signal range. Hence, the rail to rail amplifiers with wide range of signal swingare widely applied in many electronic products. However, the offset of the amplifierfabricated by the CMOS process is up to several millivolts level which seriously limits thehigh precision ampplication such as A/D converter, measuring instruments. So it is verysignificant to design low offset rail to rail amplifier.In this thesis, the theory and architecture of a rail to rail operational amplifer are detailyanalysed, and a rail to rail operational amplifier is designed, in which the band-gap voltagesource, current controlled oscillator, differential input stage, transconductance control circuit,classAB output stage, and chopper circuit are designed respectively. At the same time, theESD protection circuit is also designed. The costant transconductance is achieved by selectingthe maximum current technique and a lower offset of rail to rail amplifier is successfullydesigned by using the chopper technique. The performance parameters of the amplifier issimulated by using Hspice based on UMC0.35μm CMOS process model under differentprocess corners and temperature. The simulation results show that the unity gain bandwith is3.6MHz, the gain is116dB, the variation of transconductance is less than8%, the offsetvoltage is less than57μV, and the current is290μA. It indicates that the high gain, constanttransconductance, low offset and low power is achived for this amplifier. The layout design ofthe amplifier was analyzed after the device size of the amplifier was determined. The items oflayout design such as the match of the MOS, resistor and bipolar are briefly discussed as well,and the layout of the amplifier is designed. Finally, Postlayout simulation are briefly analysed.