Silicon Based Millimeter Wave Frequency Multiplier Chip Research

Future wireless communication systems need to support higher data rates.One of the main technological approaches to achieving gigabit per second(Gbps)rates is to take advantage of the large bandwidth available in the millimeter-wave(MM-Wave)band.At the same time,with the continuous progress of today's semiconductor technology,transistor cut-off frequency,power consumption and other properties continue to improve,promote the millimeter wave circuit and system in radar,communication,imaging and other strategic areas have been rapid development.In these millimeter-wave circuits and systems,the millimeter-wave frequency synthesizer is the core module,which directly affects the performance of the system.For example,its phase noise directly affects the resolution of millimeter-wave radar,and its frequency modulation range limits the maximum use bit rate of the communication system.In millimeter-wave frequency synthesizer,it is very challenging to realize high frequency output directly,and frequency doubling link is an important means to alleviate the challenge,which can effectively realize frequency doubling from lower frequency band to higher frequency band.This paper focuses on the frequency doubling link in the millimeter-wave frequency synthesizer,and designs and validates the 40 nm and 180 nm CMOS processes.In this paper,we analyze and compare two different schemes of generating MMW frequency synthesizer: VCO directly generating the target frequency and VCO cascade frequency doubling link through low frequency VCO.For the first scheme,the deterioration of the passive device in the millimeter-wave frequency band,the enhancement of the coupling ability between the metal and the substrate of the high-frequency signal,and the frequency traction of the VCO at the same frequency are all great challenges to the design.The second scheme can reduce its influence to a certain extent.This paper will mainly design the two and three frequency doubler in the architecture.For passive devices,the optimization scheme and application of inductor and transformer are introduced.For inductors,a more suitable model for theoretical calculation and design optimization is introduced based on the definition of S parameter,and the inductor layout is optimized accordingly.For the on-chip transformer,the design idea of gain enhancement and fourth-order coupling resonator is proposed,and the influence trend of each parameter of the resonator is analyzed and simulated.Finally,according to the disembedding structure,the flow sheet of the transformer was tested under the 180 nm process.For the doubler,two structures of push-push-pair and injection lock double doubler are designed,in which the injection lock double doubler adopts the fourth order resonator to expand the bandwidth and uses the transformer indirect coupling to reduce the degradation of the fieldeffect pipe source.Finally,the double frequency doubler designed in this paper realizes the locking range of 10.3GHz-13.6GHz under the input power of-4dBm@12GHz;For the tripler,a basic frequency suppression differential third harmonic generator is proposed based on the Cas Code structure.Compared with the traditional Cas Code structure,the basic frequency suppression ability of about 8dB is enhanced.Pseudo-differential neutralized common source circuits are used in all power amplifier stages of the frequency doubling link,and inter-stage matching and power matching are carried out by transformer structure at all levels.All the circuits have completed the electromagnetic simulation of the whole layout.Finally,the 140GHz/210 GHz doubler and tripler frequency point links based on single VCO are designed and simulated in the 40 nm process.Power distribution is realized based on transformer coupling structure and is isolated by buffer stage.