Research On Key Technologies Of High-Performance Silicon-Based Millimeter-Wave Frequency Synthesizer

Millimeter-wave and sub-millimeter-wave frequency bands have attracted extensive research due to their large available bandwidth,and the development of CMOS technology has made it possible to design low-cost CMOS millimeter-wave and submillimeter-wave integrated circuits.Different frequency bands are used in different scenarios according to their characteristics.Whether it is a high-speed wireless communication system or a radar system,a frequency synthesizer is required to provide the local oscillator signal,and its performance directly affects the performance of the system.Therefore,for popular applications such as 24 GHz short-range radar,60 GHz high-speed wireless communication and THz imaging radar,this paper focuses on the performance improvement technology of frequency synthesizers,and completes the design of three phase-locked loop frequency synthesizers based on CMOS technology.The main contents and innovations of the paper are as follows:1.This paper firstly gives an overview of the frequency synthesizer,discusses the key role of the main performance indicators of the frequency synthesizer for millimeter-wave and submillimeter-wave wireless systems.The basic structure and working principle of three commonly used phase-locked loop frequency synthesizers are introduced.The mathematical model,loop stability,phase noise and spurs of each module of the loop are analyzed,and the realization method of the??fractional phase-locked loop is emphatically introduced.The principle of the subsampling phase detector and the theory of injection locking are introduced.2.The 24 GHz multi-function radar system with short detection range and simple structure is analyzed,the structure and design index of the FMCW/Doppler dual-mode frequency synthesizer are formulated,and the novel four-coil transformer-based VCO and the LO distribution network is proposed.In FMCW mode,the??Frac-N CPPLL-based based frequency synthesizer outputs the FMCW triangular chirp,the influencing factors of rms FM error are analyzed,and the optimization scheme of chirp linearity is proposed.In Doppler mode,the loop is turned off,except VCO.The inner module adopts 8-bit DAC and temperature sensor to ensure the accuracy of the VCO output frequency.The chip test results show that the dual-mode frequency synthesizer can achieve a chirp bandwidth of 1.25 GHz in FMCW mode,the rms FM error is 68.8 k Hz,and the phase noise at a frequency offset of 100 k Hz is better than-78.54 d Bc/Hz.The spur is better than-55 d Bc,the power consumption is 92.1 m W.In Doppler mode,it can accurately output 24.125 GHz,the frequency drift between-40?120?is 27 MHz,and the power consumption is 20.1 m W.Related paper has been published to TCASII on March 16,2022.3.The 60 GHz high-speed wireless communication system is analyzed,and the structure and design index of the ultra-low jitter frequency synthesizer are formulated.The sub-harmonic injection-locked oscillator and the injection-locked"2×2"frequency multiplier chain are designed,and the sub-harmonic injection-locked frequency synthesizer is designed based on the sub-sampling PLL and the auxiliary FLL.The VCO phase noise and the noise contribution of the sub-sampling phase detector/charge pump to the loop are effectively suppressed.The proposed injection-locked“2×2”frequency multiplier chain further broadens the locking range while taking into account the low phase noise and high output power of the injection-locked frequency doubler,and also optimizes the phase of the high-frequency injection-locked frequency doubler.The chip post-simulation results show that the degradation of the fundamental phase noise and spurs by the frequency doubler chain is less than 14.28 d B at different process angles at 27°C.The frequency synthesizer has a locking range of 54.48?70.76 GHz at the TT corner,the phase noise at 1 MHz frequency offset is less than-101 d Bc/Hz,the RMS jitter is only 41.89 fs,the spur is-79.08 d Bc,and the core power consumption is42.9 m W.4.The 0.25?0.40 THz imaging radar system is analyzed,and formulate the structure and design index of FMCW high-performance frequency synthesizer according to the analysis and practice of the above two chips on the performance improvement technology of jitter and chirp linearity.Based on sub-sampling PLL and FLL,combined with digital time converter and"Zig-Zag"VCO with continuous frequency switching,the design of FMCW high-performance frequency synthesizer is proposed.The three operating modes of the swept-frequency SSPLL are described in detail.The proposed"Zig-Zag"VCO is continuously tunable over the output frequency range,using a gain calibration block to optimize chirp linearity.The chip post-simulation results show that when the frequency synthesizer works in fractional mode,the locking range at TT,27°C,is 20.2?34.5 GHz,the phase noise at 1 MHz frequency offset is less than-110 d Bc/Hz,the RMS jitter is 58.2 fs,and the reference spur is-74.57 d Bc.It achieved an rms FM error of 121.4 k Hz over a 12.5 GHz chirp bandwidth,the FOM_chirpis only 0.001%,and the core power consumption is 49 m W.This frequency synthesizer simultaneously achieves ultra-low jitter,large chirp and high tuning linearity.Related paper has been accepted by ISCAS 2022.