| Feedback shift register is the critical block of stream ciphers. Traditionally, cryptography can be implemented with two methods: one is directly in hardware, such as ASIC, the other is in general processor. As to ASIC design, the operation speed can achieve wonderfully high level, but the adaptability is relatively poor, the design couldn't meet various needs of stream ciphers. Adversely, general processor has sufficient flexibility, but the problem of which is low executive performance, it couldn't satisfy the needs of network communication. Aiming at the above contradiction, this thesis adopted reconfigurable and parallel technology to design a feedback shift register hardware structure with the tradeoff between the flexibility and high performance, which could not only support different feedback shift registers of stream ciphers, but also meet requirement of high performance.Based on the analysis of stream ciphsers, this paper systemically summarized the basis structure features of feedback shift registers, combining with stream cipher models based on feedback shift registers, taking the flexibility and high performance as the starting point, the paper summarized the operation characteristics, analyzed the reconfigurable and parallel element of feedback shift registers comprehensively.Based on the characteristic of feedback shift registers, the paper presented reconfigurable and parallel structure targeted at linear feedback shift register and nonlinear feedback shift register, which could meet requirement of random length and taps position, accomplish parallel generation of state and output sequence.Combined with the features of stream cipher models, this paper presented the reconfigurable parallel feedback shift register structure targeted at feedforward, clock-controlled and shrinking stream model respectively, accomplished high performance and flexible operation in different stream cipher models.As to the reconfigurable parallel feedback shift register structure, it is implemented and simulated on FPGA successfully. Finally, synthesis of the design has accomplished in 0.18μm CMOS process, and the performance of the design is compared with those of implementations.In short, this reconfigurable parallel feedback shift register structure has the higher flexibility and high performance. It can flexibly and effectively implement feedback shift register. |
