Logic Circuit Failure Probability Evaluation And Critical Gate Location

Over the past few decades,the advancement of the CMOS(Complementary Metal Oxide Semiconductor)manufacturing process has been the main reason behind the improvement of semiconductor device performance.As the feature size of CMOS further decreases,the integration of devices has improved and the threshold voltage has reduced,these developments have improved the performance of CMOS devices,but also introduced reliability issues.The large scale of the device substantially increases the probability of random fluctuations of impurities and component faults in the manufacturing process,which exacerbates circuit failure.Process fluctuations,aging effects,and the impact of external radiation lead to more serious instability among circuit elements,which brings great challenges to reliable circuit design.The large number of reconvergence fanout structures that are ubiquitous in logic circuits are the biggest obstacle to rapid analysis and accurate judgment of failure probabilities.The signal correlation caused by reconvergence fanout leads to difficulties in node probability calculation,circuit test generation,testability design,failure evaluation,and critical gate location.If the signal correlation problem can be solved accurately and efficiently,it will be of great significance to the development of the field of IC design and testing.(1)Aiming at the failure probability evaluation of large-scale circuits,this paper proposes a logic circuit failure probability evaluation method based on correlation separation.This method can effectrvely deal with the signal correlation problem caused by the reconvergence fanout structure,separate the correlation of the reconvergence fanout signal,and realize the accurate evaluation of the circuit failure probability.Experiments show that the accuracy of this method in evaluating the failure probability of logic circuits is greatly improved compared to other evaluation methods.Compared with the accurate analysis method,its time consumption or space consumption is much smaller,and it can realize the effective calculation of VLSI.(2)Aiming at the location of the gates of the circuit,this paper proposes a fast and accurate method for locating the critical gate of the logic circuit.For a single specific input vector,this method proposes a corresponding vector critical gate location method,which can accurately locate the set of vector critical gates corresponding to the vector;for all input vectors of the circuit,this method proposes a circuit critical gate location method,which can locate circuit critical gate for more input vectors of the circuit.Experiments have proved that compared with other critical gate location methods,this method has great advantages in the time consumption of locating critical gate,and has high accuracy.