Design And Research On Four-word-burst QDR SRAM Physical Transfer Layer Module

With the continuous development of integrated circuits,the frequency and I/O bandwidth of microprocessors is increasing,it requires a higher data transfer rate of the memory to meet the needs of the memory access.SRAM memories which are widely used in military microprocessors and aerospace electronic systems are also facing a bottleneck of insufficient speed of transmission rate.QDR SRAM memory as a new solution of the bottlenecks in access rate of static memory also has extensive research and application value.The physical interface between external memory and controller is the guarantees of memory access for the processor.The main work and innovation of this paper is completed as follows:1?This paper is toward for a four-word burst 72Mb×36bit QDRII+ SRAM memory,the principles of reading and writing and related interface protocol requirements are studied and the implemention for the interface protocols are discussed in detail toward for the interface protocol with the controller.Divided the physical interface into clock and reset management module,write data path,address and command transmission module,delay calibration module and the read data path module and also finished the logic design and verification.2?This design uses a delay calibration mechanism and with variable delay element circuit to read data phase alignment,to ensure the reliability of data collection;Delay cell which designed in custom process using the unique anti-noise of power supply noise and inverted proportion pipe design make a stage of delay cell to achieve the delay of about 70 ps.3?Finishing the physical implementation of the module and IP encapsulation.Using a grid-like clock tree structure in physical design process and reducing the data bus arrival time deviation to ensure the accuracy of data collection;IP encapsulation work on the module to make the module can be easily applied in the SOC design and with the portability features.A four-word burst QDRII+ SRAM physical transfer layer module was completed in this paper,the clock frequency is 500 MHz,Phase-shifted clock and delay calibration mechanism are used to improve the system reliability of data acquisition in high-speed storage system.The size of the module after the overall the layout and physical design in the 40 nm process technology is 350um×640um,static power is 18.24 mW.This module which having small area and low power consumption advantages can be used as IP to integrate into the ASIC design which having a reference design and application value.