Design And Implementation Of TD-LTE Physical Layer System Based On FPGA

With the development of mobile communication technology, the third generation mobile communication network (3G) is gradually evolved to the next generation Long Term Evolution (Long Term Evolution, LTE). Compared to the3G systems, LTE system achieve much higher peak bit rate and larger network capacity with new technologies such as Orthogonal Frequency Division Multiplexing (OFDM), and Multiple-Input Multiple-Output (MIMO) system., the computational complexity of thehigh-throughput LTE system is much higher at the same time, which brings new demands on the system computation performance. Time Division Duplex LTE (TD-LTE) has advantages in flexible configuration and reciprocal uplink downlink channel, it has become one of the two major LTE modes.The traditional ASIC-based solution of eNode B in LTE system has disadvantages in long development cycle and large research costs, while the solution that FPGA cooperate with DSP chips requires high inter-chip interfaces throughput, and the system-level verification and testing has a lot of difficulties. With the development of the manufacturing technique in FPGA, FPGA chips are now contains much more DSP slice, which improves the computing performance of the chips. FPGA-based SoC architecture has become a trend of embedded system, and a plenty of functional IP design libraries makes it much easier to develop a complex system. All these conditions make it possiable to implement the physical layer processing of LTE all in FPGA chip. By using FPGA to implement LTE physical layer system, it can achieve the high computing throughput comparable to with the ASIC chips, and also have a short development cycle and a low research costs. It has become a new trend of LTE eNode B system development. Design and implemention of FPGA-based TD-LTE physical layer system is studied in this paper.The design and implemention of TD-LTE eNodeB physical layer system based on FPGA SoC architecture is discussed in this paper. The detail design of hardware and software framework and key algorithm of LTE Physical Uplink Share Channel (PUSCH) link system are proposed. A20MHz LTE PUSCH link system based on Xilinx ML605FPGA development board and ADI FMCOMMS1-EBZ RF development board is developed. The design of TD-LTE downlink framework and time division duplex scheme is discussed. Each functional module of the system is fully verified and tested. The system-level OTA (Over the Air) test is performed. The results show that the system meets throughput and performance requirements of the20MHz TD-LTE system, and the data transmission by the system over the air is fluent and stable...