Design Of Quad-SPI Controller Based On AHB And UVM-based Verification

With the rapid development of modern information technology,such as AI,Io T and 5G technology,the amount of data processing has greatly increased.As the carrier of data storage,memory plays an important role in today's information technology industry,among which Flash memory is widely used because of its excellent characteristics such as large capacity and fast access speed.In embedded systems,Flash is usually used to store operating system,application software and other information,and its interaction with CPU is realized through on-chip Flash controller.Therefore,the function of the Flash controller determines whether the CPU can successfully access and how to access the external Flash.On the other hand,with the increasing scale of integrated circuits,the risk and cost of chip failure are getting higher and higher,and verification plays an increasingly important role in the chip development cycle.UVM provides a verification platform development framework with System Verilog class library as the main body.Users can use its reusable components to build a functional verification environment with standardized hierarchical structure and interfaces,thus improving the verification efficiency and shortening the development cycle.it is suitable for verification of large-scale and high-complexity chip.In this thesis,a design scheme of Quad-SPI Flash controller based on AHB bus system is proposed and its function is verified based on UVM.In order to solve the problem of slow transmission rate of traditional SPI interface,the Quad-SPI interface designed in this thesis can effectively improve the transmission rate,and it is also compatible with traditional SPI and Dual SPI mode.The Quad-SPI can read and write Flash through indirect mode.Aiming at the CPU-time-consuming operations such as Flash programming and erasing,a polling mode is designed,which enables Quad-SPI controller to automatically obtain the status of registers in Flash according to a certain period and initiate an interrupt request when the expected status is matched,thus saving CPU resources.In So C design,the capacity of onchip memory is usually relatively small for saving the area.In order to meet some application requirements with high memory capacity,the memory can be expanded by mapping the external Flash memory space to the internal memory space.Therefore,the Quad-SPI controller designed in this thesis supports the memory mapping mode,so that AHB host can directly access the Flash memory space through the mapping address.In addition,many operations of Quad-SPI controller are related to register configuration.To prevent Flash access errors and even damage internal data of Flash due to software mismatch,corresponding circuits are designed to check possible incorrect configuration.When configuration errors occur,the current operation can be suspended and errors can be reported,which improves the reliability of the controller.UVM has a standard hierarchical structure,but it also has a high degree of flexibility.To improve efficiency in the verification process and build quickly a hierarchical and reusable UVM verification platform for the Flash controller,AHB VIP is analyzed in this thesis and integrated in the verification environment,thus saving time for developing AHB transaction agents.RAL model is introduced and random constraint verification strategy is adopted to simplify verification process and improve verification efficiency.The verification progress is measured by the coverage rate,and the functional coverage model is compiled.Finally,the functional coverage rate is 100%,and the code coverage rate is 97.7%,reaching the verification target.At last,the reading and writing test of Micron MT25QU128 ABA SPI Flash model is completed,and the results show that the Flash controller designed in this thesis can correctly complete its functions.