The Function Verification Of Flash Based On UVM

In recent years,with the development of the IC(Integrated Circuit),IC's arithmetic capability has got a great success.While the Integrated Circuit became huger and more complex,the verification of the IC became the bottleneck throughout the entire design process.As we known,effective verification not only ensures the correctness of the implementation,but also improves the design productivity,which is a guarantee to reduce the time to market.So now,in order to build a faster and most compatible method which also can be widely accepted by most manufacturers,and can make the verification to be more automatic,more flexible,more easily to interaction,to get more full-scale verification for the daily strong DUT(design under test),the study use the main verification methodology based on company project complete and improve the verification environment.The major standpoint of this study is to introduce the functional verification based on UVM.Firstly,the current study in the background,goal and significance is surveyed,showing the importance of the verification.Later,the study analyzes and concludes the current mainstream verification techniques,the practical methods are presented,which included using CRT(constrained random test)instead the directed test;using the functional coverage as a measurement;using the VUM methods based on System Verilog improve the verification environment;using SVA,etc.According to the normal project schedule,the study firstly summarized the behaviors of the DUT,and completed the test plan.And then,the test bench has be built and self-checked.With the results,the test bench got further optimized.In the study,the sequences are divided into base sequences and complex sequences,and the complex sequences are made up of bases sequence and self-defined task.And in the test bench,the SVA is used to build the analogy sequence.With the SVA,the analogy sequence could be built easily,and it also improved the completeness and reliability of the test bench.Finally,the article uses the coverage to measure the test cases.According the coverage,the Verification Engineer could adjust the test environment,and make it more completeness.Absolutely,the study got the one hundred percent coverage by adding direct tests.So,we could know that the study verification work have completed,and the test bench has a high quality.