The Optimization Scheme Of DSP Instruction Set Simulator

Instruction Set Simulator is a software used to simulate the Central Processing Unit (CPU) architecture, and it is usually designed by high-level programming language. Instruction Set Simulator has played an important role in the process of embedded system design. For example, during the CPU architecture design, it can be used to evaluate whether the architecture is appropriate. During the CPU function verification, it can be used to judge whether the CPU works without mistakes. During the development of system software, it can be used to debug the software before the real CPU is produced. Although it takes a lot of advantages, the use of Instruction Set Simulator has been restricted due to its simulation speed.In order to improve the simulation speed of Instruction Set Simulator, this paper uses the reprocessing of function block, pre-decoding, multi-thread, dynamic mode scheduling and automatic generation of dynamic libraries to design and implement a simulation acceleration multicore DSP Instruction Set Simulator (Optimized Instruction Set Simulator, OISS) based on the original interpretation multicore DSP Instruction Set Simulator called Diamond_ia. The decoding time of Diamond_ia has been the most time-consuming part during the simulation, thus the pre-decoding is used to decode the target program, which can avoid the unnecessary repeated decoding existed on the Diamond_ia. In the executing phase, dynamic mode scheduling is introduced to accelerate the Instruction Set Simulator. Dynamic mode scheduling involves the switch of interpretation simulation mode and dynamic link library mode. Diamond_ia needs to decode and execute every instruction, which leads to the low efficiency; Dynamic link library mode improves the speed of Instruction Set Simulator using the dynamic link library generated in the sub-thread phase,and skipping the original process of decoding and executing as well.The novel Instruction Set Simulator runs on a Linux sever with Intel Xeon E5520, 2.27GHZ CPU clock frequency,8GB memory. The validity of the novel Instruction Set Simulator can be verified by comparing the running results of the same target program on the novel Instruction Set Simulator and host machine; And the simulation increase can be verified by comparing the running results of the same target program on the novel Instruction Set Simulator and Diamond_ia. According to the testing results, the proposed Instruction Set Simulator runs 60% faster than the previous one.