Research And Design Of Low Power Successive Approximation Register ADC For Implant Biochip

In recent years,the rapid development of artificial intelligence and integrated circuit has had a profound impact on health medicine.Machine learning can use a large number of clinical data of patients to analyze their condition accurately,and intelligent computer systems can provide treatment programs for health professionals.Smart medicine is deeply integrated in the fields of electronic information,biomedicine and data analysis,which is of great significance in leading the future medical era.As the hardware carrier of smart medicine,implantable biomedical chip has gradually become a research hotspot in recent years.Implantable biochips need to be implanted into the organism to obtain the physiological parameters of the subjects,so they require lower power consumption and smaller area.As an indispensable module in this kind of chip,the performance of the analog-to-digital converter(ADC)will directly affect the performance of the chip.The successive approximation register(SAR)ADC,which has the characteristics of low power consumption,moderate accuracy and small area,is very suitable for such low-power applications.This paper aims to design a 10 bit 10 KS/s low power SAR ADC for implantable biochip.This paper focuses on the four key modules of SAR ADC,including sample-and-hold switch,comparator,SAR control logic and DAC capacitor array.The corresponding low-power technology is summarized,and the design and implementation scheme is proposed.In this paper,the bootstrapped sample-and-hold switch is used to improve the situation that the on-resistance of traditional MOS switch will vary greatly with the change of input voltage,which has high linearity.In this paper,the two-stage preamplifier dynamic comparator is used to reduce the input offset voltage and noise,and balance the power consumption.In this paper,The synchronous semi-dynamic SAR control logic circuit is adopted,which is composed of D flip-flop,latch and logic gate circuit.The unit logic gate circuit adopts stack structure to reduce the power consumption of the circuit.In this paper,based on the V_CM-based switching algorithm,a multi-segmented DAC capacitor array with upper plate sampling and"1+1+8"is proposed.Its progressiveness has the following four points.First,the capacitor array leads to the input common mode voltage of the comparator not changing with the voltage switching of the bottom plate of DAC capacitor array,which improves the stability of the system.Second,the power consumption of the upper plate sampling is lower than that of the bottom plate sampling.Third,compared with the traditional binary weight DAC structure,the number of unit capacitors in the array is greatly reduced and the power consumption is reduced.Fourth,compared with the segmented DAC structure,the attenuation capacitor is an integer unit capacitance,which improves the circuit accuracy.In this paper,the circuit design and layout drawing are realized based on 55nm CMOS process,and the layout area of SAR ADC is 185?m×107?m.When the power supply voltage is 1 V,the sampling frequency is 10 KS/s,and the input sine wave signal frequency is 4.678 KHz,the simulation results show that the ENOB is 9.37 bit,the power consumption is 75.29 n W,and the Fo M is 24.33 f J/conversion step,which meets the design goal of this paper.