A transceiver design for implantable medical devices

In recent years, implantable devices and wearable devices are extensively applied in clinic to assist patients either to substitute the missing function of a damaged organ or to alleviate and remedy the disease progression of a malfunctioning part in the body. It has become one of the hottest topic in the intersection of electronic and medical. A number of products and applications such as brain pacemakers, retinal implants, wearable blood pressure monitors and blood glucose detectors have been released into healthcare markets. They are often used with operational software applets installed on smart phones/ tablets in order to monitor or assist the therapy of epilepsy, amblyopia, and even heart diseases. One of the key challenges of developing these devices is to reduce both the device size and power consumption while improving data rate and power efficiency. These two requirements are difficult to be simultaneously achieved because increasing data transfer rate normally increases the power consumption and enlarges the device size.;In this research, we propose a transceiver design for an implantable medical device that utilizes inductive coupling coils for data and power transmission. A Class E power amplifier was employed to amplify and transfer power from the transceiver side (external device) to the receiver side (internal implant). And then with a Load Shift Keying (LSK) demodulator --- a particular scheme of Amplitude Shift Keying (ASK) which has a higher data recovery efficiency compared to Frequency Shift Keying (FSK) structure for digital signal transmission --- the biological data captured by the implant were transmitted back to the transceiver. The LSK demodulation technique allowed power and data to be transferred simultaneously through one single inductive link. It could work under a variety of modulation indexes and different coding/decoding protocols. Furthermore, it enables us to reduce both the power consumption and the device size of the transceiver. The circuits were fabricated in 180nm CMOS process technology and a prototype was designed to demonstrate the performance of the proposed demodulator. Measurement results indicated that the circuit could support the power carrier signal of different frequencies and data rates. The core area of the chip was 750mum x 800mum and the achievable minimum modulation index of the prototype was 5%, whereas the supported data rate was 1 Mbps. With a 1.65V power supply the total current consumption was 3.6 mA.