Research On High Performance Queue Management And Scheduling

With the further popularization and development of network technology,there are more and more network services which bring better experience to people.People demand more and more network bandwidth.As the core device of the switch or router,the performance of the switch or router is the key to restrict the throughput of the network.In order to support the needs of the users,more and more protocols are deployed on the switch,and the design is more and more complex.Because of the closed characteristics of network devices and the independence of different manufacturers and equipment,it is becoming more and more difficult to deploy new applications and real-time control of network traffic on the existing network.A new cyber architecture named Software defined Networks makes network more flexible and expandable,and provides a new idea for the network management by separating the data plane and control plane of swtich.Among them,Openflow protocol is the most widely accepted communication protocol between controller and switch.However,the precisely control on how to forward data flow by means of application of Software Defined Networks is at expense of increasing quene size by large.In the Highspeed data forwarding system,how to manage and schedule massive data stream queues is of great significance for improving the performance of the forwarding system.Based on the project undertaken by our laboratory which named “Research on the architecture and key technologies of software defined network data forwarding system”,this thesis focus on research of high performance supporting 100 Gbps in quene management and multi-level queue scheduling algorithm.Firstly,this thesis will introduce the background and development of Software Defined Networks,and then,based on the project requirement,a general summary is about a design of Software defined Networks data forwarding system based on Openflow protocol.Secondly,a parallel non-conflict queue management scheme is proposed given the fact that in existing queue management scheme,there is a clash and speed-limit of avoiding getting out of team if enqueue and dequeue is frequently switched as well as it happening simultaneously.By increasing conflict detection,this scheme corrects the conflict update information without the introduction of the operation cycle,and ensures the processing performance.The maximum support rate for each queue scheduling is up to 20Gbps.Besides,a multilevel Qo S scheduling mechanism is designed and implemented,and a partial scheduling algorithm is improved to solve the problem of limited cycle time and limited scheduling performance due to increasing quene size.Finally,to verify the correctness of the scheme,on the one hand,a comprehensive simulation is used by Xilinx Vivado tools and Modelsim.And part of functions are tested on Xilinx VC709 FPGA development board.On the other hand,the queue management scheme is applied to design of 10 G HIMAC and in that hardware platform.Further tests verify the correctness of queue management scheme.