Face Detection Based On FPGA And MTCNN

Nowdays,face recognition is a research hotspot in the field of computer vision and machine learning,and it has broad applications in community management,public security,livelihood industries and so on.As a key part of face recognition,face detection has a major influence on the result of recognition,so the research is of far-reaching significance.MTCNN,as known as multi-task cascaded convolutional networks,is a convolutional neural network model that can process face detection and alignment at the same time.Compared with other face detection neural network models,MTCNN can accepet input images of any size,has high detection accuracy,and can also capture key points of the face.Recently,neural network models are mostly implemented based on GPU or CPU,which are large in size,high in power consumption and high in cost,while FPGA has the characteristics of high flexibility,low risk and low cost.In meeting the requirements of the actual face detection system's size,detection range,adaptability and others,this thesis chooses Zynq-7020 FPGA to realize face detection based on MTCNN.The main work of this thesis includes:(1)Study the model of MTCNN,and allocate reasonable software and hardware tasks according to the characteristics of the three networks that compose MTCNN.Extract and statistically analyze MTCNN model parameters.With the consideration of on-chip calculation and the loss of quantiaztion and other reasons,choose FP32 implemantation scheme.(2)Use Xilinx HLS tool to design the hardware accelerator for FP32 convolutional neural networks.The hardware accelerator can perform 1×1,2×2,3×3convolution with a step size of 1,2×2,3×3 maxpooling with a step size of 2,PRe LU activation,and reuse convolution design to achieve full connection.The burst transmission of input feature maps and weights is used to speed up data loading,and the strategies of block buffering,pipeline and others are taken to accelerate calculation.(3)Based on Zynq-7020 FPGA,build a Linux system and write C++ programs for the design.With the use of hardware accelerator,receiving images by camera,NFS services or other ways,the design of this thesis coordinates software and hardware to finish forward propagation of MTCNN,which realizes face detection and key points of face capture.(4)Use the on-chip logic analyzer IP to perform waveform analysis for the hard accelerator,and debug softwore.The face detection data set and benchmark namely FDDB is used to generate the ROC curve for comparison with the original model based on Caffe.Though recall rate drops when the design of this thesis is compared with the original model,it satisfies the actual use.When inputing a 640×480 image and detecting the minimal face size of 60×60,the frame rate of single face detection is about 1.25 fps.Compared with the PS side,the speed is about 74 times faster.The on-chip power is about 2.34 W,and the resource consumption is less than that of the same type of design.