Design And Implementation Of Convolutional Neural Network In ZYNQ

With the breakthrough improvement of computer computing power,Convolutional Neural Network(CNN)has been maturely used in security monitoring,speech semantic recognition,image classification,target recognition,intelligent control and other fields.In recent years,the main platform used for neural network training and inference is GPU,but GPU platform is expensive,high power consumption,not suitable for embedded and other micro devices,while Field Programmable Gate Array(FPGA)platform has parallel high-speed computing,low power consumption,and low price.Suitable for features such as micro equipment.Therefore,an CNN acceleration platform based on FPGA came into being.This article first introduces the layer structure of CNN,including convolutional layer,pooling layer,fully connected layer,etc.,and analyzes the feasibility and advantages of FPGA to accelerate CNN.According to the characteristics of the parallel operation of multiple convolution cores in the CNN,combined with the advantages of FPGA platform suitable for high-speed parallel operation,a method of using FPGA to accelerate the convolution operation part is proposed.Secondly,according to the characteristics of convolution operation multiplexing,the data multiplexing method is adopted,and the parallelism of convolution operation is divided according to the size of hardware resources.Then,aiming at the problem that the pure FPGA structure is suitable for parallel acceleration calculation but is not good at embedded control,a heterogeneous acceleration method is proposed.This method uses ZYNQ series FPGA,the chip is ARM+FPGA structure,the neural network is divided into two parts of convolution operation and fully connected operation.This method uses the FPGA side to accelerate the convolution operation part that requires high parallelism,and the ARM side completes the operation control,data transmission and full connection layer.This heterogeneous acceleration method greatly shortens the development cycle and reduces the development difficulty.In addition,the experimental results show that the method can improve the speed and has versatility.Finally,the design of convolutional neural network is realized by taking digital handwriting as an example.In this design,a multiplexed convolution operation module was built on the FPGA side of the ZYNQ platform,and a control module and a fully connected layer operation module were built on the ARM side.It has been verified that the heterogeneous acceleration platform can complete the recognition of digital handwriting.The power consumption of the entire algorithm project is 1.856 W,the calculation time of a picture is 87 us,and the accuracy rate is 91%.The experimental results show that the acceleration platform is ensuring its accuracy.At the same time,it has faster speed,lower power consumption and versatility.Compared with other platforms,this platform is obviously more suitable for accelerating CNN.