The Algorithm Design And FPGA Verification Of Face Detection And Recogniton Based On 8Bit Quantization Neural Network

The face detection and recognition technology is user-friendly and widely used.Today,it has become one of the most important biometric recognition technologies in social life.The face detection and recognition method based on deep convolutional neural network has better accuracy and scalability than traditional methods,but its storage,transmission and calculation costs are also higher.The numerical quantization method can reduce the running cost of the deep convolutional neural networks,and with the optimized hardware design,it can achieve higher processing speed under limited resources.If the accuracy of the networks can be maintained at the same time,it makes it possible to implement an efficient face detection and recognition system at the terminals.It is also a key technology for the next generation application scenarios such as intelligent city,AI-IoT and so on.The representative methods of face detection,face recognition,neural network quantization and hardware acceleration are summarized in this thesis.Then,the quantized data distribution form of the DoReFa-Net algorithm is changed to improve the storage utilization rate of the fixed-point quantization model.The test results show the 8-bit quantization precision can maintain the accuracy and obtain significant compression and acceleration efficiency.The end-to-end 8-bit quantized face detection network based on YOLO algorithm obtains high accuracy and fast face detection speed.The 8-bit quantized face recognition network based on CenterFace algorithm with low inter-class distance and high intra-class distance,making face recognition error less,and the identification category is more scalable.On this basis,a universal FPGA convolutional neural network accelerator with low bandwidth requirement,high throughput and high resource utilization is implemented through multi-level parallel computing and data multiplexing optimization.Finally,the 8-bit quantized face detection and recognition networks and the hardware accelerator are combined and verified on the FPGA development platform.The 8-bit quantized face detection network designed in the thesis achieved 93.91% accuracy on the FDDB face detection dataset,and the 8-bit quantized face recognition network achieved 94.23% accuracy on the LFW face recognition dataset.Both accuracy quantified losses are less than 1%.Based on the quantized face detection and recognition network,the convolutional neural network accelerator can get 125 GOPS effective computing power on the Zynq XC7Z035 FPGA chip when the clock frequency is 100 MHz,and the average utilization rate of the calculation unit exceeds 80%.A terminal face detection and recognition system is designed and tested on MIZ-7035 development board.The research can provide some empirical reference for the subsequent work,such like high-accuracy or high processing speed face detection and recognition hardware acceleration research.