The Key Research On Design For Scan Chain Diagnosability For Multi-bit Scan Cell

With the increasing complexity of chip functions,more and more digital integrated circuits are used in every aspects of daily life,including mobile phones,computers,automotive chips,medical electronics,and so on.The increasing complexity of the chip has led to an increasing probability of faults inside the chip,and the difficulty of fault diagnosis has also increased.Since the beginning of the 21 st century,the feature size of chips has also become smaller and smaller,and smaller feature sizes have also aggravated the interaction between faults,making digital integrated circuit testing and diagnosis more difficult and time-consuming.As the most common testability design method,scan chain design has a very wide range of applications in the field of integrated circuit testing and diagnosis.The scan chain design improves the controllability and observability of internal nodes by transforming the internal flip-flops and connecting them in a specific way,thereby improving the testability of digital integrated circuits.However,the scan chain circuit is specially designed to improve the testability of digital integrated circuits,and its fault distinguishing ability is weak,so the diagnosability is lower.Therefore,the scan chain fault diagnosis is facing severe challenges.With the scaling in feature size,low power consumption and low area overhead are important goals for digital integrated circuit design.In order to achieve this goal,multibit flip-flops have emerged.Multi-bit flip-flops achieve reductions in power consumption and area overhead through transistor sharing and clock tree optimization.In the scan chain design,the multi-bit flip-flop is transformed into multi-bit scan cell,but the existence of the multi-bit scan cell brings new challenges to the diagnosability design of the scan chain.In order to solve the above problems,this dissertation proposes diagnosability design method for multi-bit scan cells.The main research results are as follows: On the one hand,this dissertation fully analyzes the various limitations of the multi-bit scan cell in the exchange process.On the base of the design method for diagnosability based on scan cell re-stitching,an exchange allocation scheme of multi-bit scan cells is proposed.This method greatly increases the number of fault sensitive scan cells in the scan chain circuit.On the other hand,due to the large number of scan cells in the circuit,scan compaction technology is often used in actual industrial production to compact multiple scan chains into one scan channel to reduce the amount of test data and time overhead.This dissertation also proposes a method of dividing scan channels into groups when the backend design constraints are met.This method can ensure that the scan chain circuit under scan compaction achieves the best diagnosis quality.The experimental results of the ISCAS'89 and ITC'99 benchmark circuits show that when the proportion of multi-bit scan cells in the circuit reaches 50% and a fixed fault occurs in the circuit,the average diagnosis resolution is 1.306(the ideal value is 1).For SA0 faults,the average diagnosis resolution is 1.279,and for SA1 faults,the average diagnosis resolution is 1.333.When the proportion of multi-bit scan cells in the circuit increases progressively,the average diagnosis resolution is still below 3 even if it reaches 100%.