Design And FPGA Verification Of CNN Accelerator Based On Incremental Quantification

In recent years,the accuracy of convolutional neural network has been significantly improved in the field of computer vision.However,due to its large demand for storage resources and computing power,it cannot be deployed in small equipment,so it is necessary to reduce the number of parameters of the convolutional neural network and reduce the computational complexity.Therefore,the research on quantization and hardware acceleration of convolutional neural networks has important practical significance.Based on convolutional neural network parameters exist a large amount of redundant information,the network weights are quantified by the incremental quantization algorithm in this thesis.Group quantization network weights,the group with a large absolute weight is quantified,and the group with a small absolute weight is trained to make up for the accuracy loss after quantization.Then encode the quantized weights for hardware design.In terms of hardware acceleration,according to the characteristics of the quantized weights,the convolution calculation unit is designed as a shift operation,which reduces the use of multipliers;the computing module adopts array structure and supports different data reuse modes,reduces the number of memory accesses,increases the degree of parallelism and data reuse rate,reduces power consumption and bandwidth requirements,and improves throughput.In ILSVRC2012 data set,the top-1 accuracy of VGG-16 only decreased by 0.44%.In this thesis,a convolutional neural network accelerator based on incremental quantization is designed on the Xilinx Virtex-7FPGA development board,and the VGG-16 was used as the test network to verify the overall performance of the accelerator: at a working frequency of 150 MHz,the accelerator's throughput rate was 273.6GOPS and power consumption was 6.128 W.The CNN accelerator based on incremental quantization design reduces the demand for hardware storage resources and computing power,and configurable and low power consumption.It can provide a design reference for the deployment of deep convolutional neural networks on small devices.