Design Of Sparse Convolutional Neural Network Accelerator Based On Shift Unit

Convolutional neural networks have gradually become the basis of artificial intelligence applications.However,the large amount of network parameters increases the deployment difficulty and limits application range of CNNs.How to design lightweight algorithm and high efficiency hardware accelerator has become a research hotspot.Based on the weight compression algorithm,this paper explores the network sparsity and low bit-width inference technique.We propose a lightweight algorithm which combines the weight pruning and power quantization,and use the Image Net dataset to verify the algorithm.Aiming at this algorithm,a shift unit based sparse convolutional neural network accelerator is designed.In view of the characteristics of sparse network with less weight but unbalanced operation,this paper models sparse convolutional neural networks,analyzes the impact of different data replacement strategies and parallel strategies on accelerator memory access amount and acceleration ratio,and proposes a data flow with high process engine utilization and low energy consumption.In this paper,the compressed weight storage method and index units are designed to skip invalid operation;the multiplier is replaced by shift unit to reduce the power consumption of operation unit;tiling convolution mode is supported to balance the efficiency and flexibility of accelerator;for the memory wall problem,ping-pong buffers are used to hide data transmission delay;in order to enhance data reuse,a systolic-like process engine interconnection method is proposed.In this paper,the design is realized by RTL,synthesis and physical design are finished.We analyze the power consumption and operation speed of the design.The accelerator will tape out based on TSMC28 nm process.The lightweight algorithm proposed in this paper reduces the number of weights of traditional convolutional neural network models to 28% and the weight bit width to 25% compared with the original model.With the cost of reducing the accuracy of complex tasks by about 1.4%,the demand for memory access is greatly reduced.The hardware accelerator designed in this paper has an equivalent performance of 377.1GOPS,a power consumption of 329.9m W,an energy efficiency of 1.14TOPS/W.The process engine utilization ratio is 3.1 times higher than that of other works;the memory access power and system energy consumption are low,and the energy delay product is 62.5% compared with the state-of-the-art research.