Design Of A 25Gb/s CMOS Adaptive Equalizer Integrated Cirtuit

Compared with parallel communication,serial communication has higher speed and more suitable for long distance transmission.Because of these advantages,serial communication is increasingly selected as the transmission method of I/O interfaces.Since the pin count of the I/O interface is limited by the area and trace density,it is necessary to increase the data rate on each serial link to improve the throughput of data.Due to non-ideal factors like dielectric loss and skin effect,high-speed signals passing through lossy channels will have severe attenuation and inter-symbol interference(ISI).In order to compensate for high-frequency attenuation and ISI,equalizers have been widely used in serial interface circuits.Meanwhile,equalizers should be adaptive to the changes of channel characteristics in different environments for achieving the best equalization in real time.A 25Gb/s adaptive decision feedback equalizer(DFE)with half-rate speculative structure is designed in 65nm CMOS technology.The equalizer mainly consists of the main circuits of the DFE and the adaptation engine.The main circuits include a continuous-time linear equalizer,adders,a stacked selector,current-mode logic(CML)latches and output buffers,etc.The adaptation engine included a detector composed of a sense amplifier and logic gates,a 5-bits up/down counter and a5-bits current steering digital-to-analog converter(DAC).The parallel inductance peaking technology is adopted to increase the speed of modules on the critical path for reducing the feedback delay.An improved digital structure of the adaptation engine based on the least mean square(LMS)algorithm is employed to improve the convergence of the tap coefficient.An improved f _T doubler with a passive low-pass filter is used for higher bandwidth and optional pre-emphasis.Simulation results show the adaptive DFE can properly equalize the channel with 20d B attenuation and the adaptive process can be completed within 1?s at different process corners when the input signal is 25Gb/s non-return-to-zero(NRZ)binary data with different attenuation.In post simulation,the minimum eye height of the output signal eye diagram is 222m V@FF;the maximum jitter is 10.2ps@-20d B,FF;and maximum power consumption is 121.5m W@FF.The overall layout area of the equalizer is 837?m×907?m,and the area of the core part without inductance was362?m×424?m.