| With the development of information and intelligence in society,people are paying more and more attention to the safety of data communication.In order to ensure that data is not stolen by unauthorized third parties during transmission,users usually perform some encryption processing on the data before transmission.At present,ASIC communication chips are mostly used for communication between hardware boards,among which the typical ones are Ethernet and PCIE exchange chips.In recent years,this type of chip has developed rapidly,but there are certain safety hazards in the use of specific occasions.At present,for scenarios with high security requirements,quantum encryption has been tried to introduced,but this encryption method is too complex and costly,and is not suitable for general scenarios.For the broad industrial control,power communication and other fields,large-scale commercial information security supporting program has not been proposed.In this paper,the industrial control system in the process of information transmission in the existence of security risks as the entry point,combining the encryption and chip,making use of cryptography related knowledge to improve the security of communication chip and reduce the information leakage of various security risks.The main work is as follows:This paper presents a design scheme of Ethernet physical layer secure communication.In the hardware implementation of AES algorithm encryption,by optimizing the internal logic and introducing pipeline design to ensure the high speed and security of data transmission;When designing the Ethernet physical layer chip,the physical layer structure of the chip is described in detail at first,and then the core circuit of the chip is modeled and simulated,and the function is analyzed.Finally,the chip realizes the function of data bridge communication between FPGA and optical fiber.In this paper,the optical fiber communication hardware system is built,and the optical fiber1000BASE-X working mode of domestic Ethernet chip is used to transmit the AES encrypted data.In order to ensure the reliability of transmission,a set of communication frame structure is also defined for the encryption algorithm.The Xilinx Artix-XC7A100 T encryption algorithm consumes1037 Slice LUTS and 151 Slice Registers per 14 iterations.The Sbox can consume up to 64 Slice LUTS.The power consumption of the encryption algorithm is 0.816 W,and the speed and resource consumption of the encryption algorithm have obvious advantages compared with similar research.When analyzing the performance of optical fiber secure communication system,a proprietary IBERT link test tool is used to analyze the terminal resource utilization,communication transmission rate and signal quality.The experimental results show that a total of 3608 LUT and 5733 registers are used for the logic resources of the encryption terminal,and the hardware resources are less used.The actual rate of the link is 1.25 Gbps,indicating the transmission rate is high.Moreover,the bit error rate of optical fiber transmission is only 7.677E-12,and the opening angle of eye diagram is reasonable,indicating that the signal integrity is good.Based on the work of encryption algorithm and optical fiber link design and implementation in this paper,it won the first prize in the national final of China Postgraduate Electronic Design Competition in 2019.The Ethernet physical layer chip designed in this paper has been verified in Unigroup Micro,and completed the wafer flow,sample,identification,packaging and testing. |
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