Research On Mask Stage Displacement Measurement System Architecture Based On Multi-Core Computing Board

As one of the three key indicators of the lithography machine,productivity occupies an important position in evaluating the performance of high-end lithography machines,which is directly affected by the calculation period of the mask stage displacement measurement system.Therefore,research on the mask table displacement measurement system architecture is of great significance for improving the productivity of the lithography machine.Due to the late starting and the technical blockade abroad,domestic development on the architecture of the mask stage displacement measurement system is still at a low level.Continuous development of domestic high-end lithography machines demands higher production,while the current system architecture is difficult to meet the requirement for a shorter calculation period of 50 us.In this paper,we took the mask table displacement measurement system architecture as research object,combined with the data flow of the measurement system,theoretically analyzed each link that affects the calculation cycle,and proposed a mask table displacement measurement system based on a multi-core computing board Architecture.In addition,the key technologies of the firmware architecture in multicore computing boards had also been investigated.Finally,a test platform had been established for experiments.As the comparative analysis shown,the proposed system architecture exhibited a great improvement in the calculation cycle compared with other domestic system architectures,which could meet the requirement of 50 us calculation cycle.The main contents of this paper are as follows:Firstly,we analyzed the data flow in the calculation cycle of the mask stage displacement measurement system in detail,summarized the main links that affect the system calculation cycle,and analyzed above links for the system architecture based on single-core computing boards and a multi-core computing board.Secondly,multi-core CPUs with different architectures and backplane buses had been analyzed from various aspects.Multi-core computing boards equipped with multi-core DSP and VME backplane bus interface had been selected comprehensively,and the system hardware architecture had been designed completely.Thirdly,we chose the master-slave exploitation model as multi-core firmware exploitation model,and made full use of the SYS / BIOS operating system provided by the multi-core DSP for firmware exploitation.In addition,in this paper,we conducted a comparative analysis for the inter-core data interaction method of multi-core DSP,and selected the method of using shared memory for data interaction.A mechanism for intercore data interaction was proposed in view of the data consistency in this method.Finally,the performance of the system architecture proposed in this paper was tested and compared by building a test platform.As the test results shown,the average rate of the on-chip bus used for reading and writing multi-core computing board was 163.85 Mbps and1 120.88 Mbps,the average rate of reading and writing VME backplane bus was as high as7 169.52 Mbps and 10 563.75 Mbps,and the average rate of reading and writing fiber data was 448.79 Mbps and 568.94 Mbps.In addition,the hardware-in-the-loop simulation experiment indicated that the calculation cycle of the proposed system architecture was improved by approximately 160.68%,compared with the shortest calculation cycle presented in China.The system architecture proposed in this paper met the requirement of50 us calculation cycle,while the model calculated accurately at the same time.