Development Of WR Dual-port Boundary Clock Module And Research On Networking Technology

As the system becomes more and more complex and the degree of dispersion becomes higher,higher requirements are put forward for the timeliness and accuracy of each node in the network in many fields.With the increasing complexity of the system and the increasing degree of decentralization,the timeliness and accuracy of each node in the network are put forward higher requirements in many fields.The previous methods of providing global clocks for independent communication nodes have many shortcomings.For example,when the local clock is used to obtain the time,the working environment of these local clocks is different,and the oscillation frequency is different,which will cause the global clock to be inconsistent;When GPS is used for timing,its signal covers blind spots,installation is complicated and easy to malfunction;when using the PTP protocol,the synchronization accuracy can not reach the sub-nanosecond level and other shortcomings.In order to solve the problem of multi-node sub-nanosecond synchronization timing,it is necessary to carry out White Rabbit(WR)networking technology research and develop a WR dual-port boundary clock node with time distribution and relay functions.The main research contents of this paper are as follows:(1)Theoretical research on WR technology.Including synchronous Ethernet,precise timing protocol(IEEE1588 v2),building a WR link model to analyze the total delay of the round-trip links between the master and slave nodes,and digital phase measurement technology.(2)Research on cascading networking technology.Multiple WR-BC-DP modules can be serially connected with each other to form a chain topology,and multi-node cascading time transfer can realize networking.Summarize how the synchronization accuracy has changed and deteriorated after the first-level node,the second-level node,and the relay.Based on the study of the second-level node,the empirical theory is used to calculate the synchronization accuracy of more nodes and deeper levels.(3)Development of WR dual-port boundary clock module(WR-BC-DP).The board adopts the design method of backplane + module,which separates the highly multiplexed WR interface function part and designs it into a module(ie,WR synchronization module),and realizes routing and time distribution between modules through the backplane.Developing multi-node sub-nanosecond synchronization timing boards based on WR technology,including backplane design,WR synchronization module design,embedded software design,and FPGA HDL design.(4)Time distribution experimental research.Use the developed board to build a time distribution experiment test platform to study the synchronization accuracy test experiment of multi-node time distribution.The synchronization accuracy(mean value)of the primary node is 165.4ps,and the synchronization accuracy(standard deviation)is 37.8ps.After passing through the secondary node,the synchronization accuracy is degraded by 143.0ps and the synchronization accuracy is degraded by10.1ps.