Design And Implementation Of Transmitter Based On JESD204B Protocol

With the rapid development of microelectronics technology,the resolution and conversion rate of data converters(ADC/DAC)have been continuously improved,and the data transmission rate has increased sharply,which puts forward higher requirements for communication interfaces.In the past,converters usually use CMOS and LVDS parallel communication interfaces.With the improvement of converter performance,problems such as too many pins,high crosstalk,high power consumption,and complex PCB wiring are particularly prominent,which limit the development of integration of high-speed data conversion systems.In order to meet the needs of converters for high-speed data transmission,the JEDEC organization released the JESD204B serial communication protocol.Compared with CMOS and LVDS interfaces,serial communication interface based on JESD204B has the advantages of fewer pins,low power consumption,high flexibility,support multi-channel,multi-link transmission and deterministic delay functions.Each channel is recommended the maximum data transmission rate has reached 12.5 Gbps,which can effectively reduce the design difficulty of the data conversion system and conform to the trend of miniaturization and integration.In recent years,JESD204B has gradually become the mainstream interface protocol for high-speed converters.At present,the research and application of JESD204B protocol abroad has become mature.The domestic research on the protocol started late.With the gradual deepening of the research,there have been more application cases implementing the protocol on FPGA,but fewer cases of completing circuit have been tape-outed.According to the research and analysis of the JESD204B protocol,this paper designs and implements a transmitter based on the protocol,and completes the ASIC tapeout test.The main contents of this paper are as follows:1.Briefly introduce the development and differences of the four versions of the JESD204series protocol,focus on the content of the JESD204B protocol,and analyze the working principles of the application layer,transport layer,data link layer and physical layer.2.Developed the overall design architecture and performance indicators,and use Verilog HDL to design the functions of each layer of the protocol at the RTL level.The transmission layer has completed link parameter checking and related clock and control signal generation,and proposed a three-level mapping processing method to realize the sampling data framing function of 8 link configurations;the data link layer follows the scrambling and code groups The sequence of synchronization,initial channel synchronization,user data transmission and character replacement,and 32b/40b encoding is completed in sequence;the physical layer has completed the design of frequency division clock generation and three-level parallel-to-serial conversion.Use VCS simulation software to simulate the RTL code of each module,and use HSIM simulation software to simulate the physical layer analog circuit.The simulation results show that the functions of each module are normal,and each layer of the transmitter can realize the expected function.3.Build a UVM verification platform,use RX IP and the transmitter of this article for overall simulation verification.The simulation results of the link synchronization and data transmission process,as well as the comparison results and verification reports of the sampled data at the sender and receiver are given.The verification result shows that the transmitter functions normally in 8 link modes and can establish a link correctly for data transmission.4.Based on 65 nm CMOS process,use Design Compiler software to logically synthesize the transmitter RTL code.The comprehensive result shows that,under the set frequency of312.5 MHz,the logic circuit resource area of the transmitter is 98804.35?m~2,and the power consumption is 52.7 mW.Use Virtuoso to design the layout of the analog-to-digital converter containing this transmitter,the result shows that the area of the logic circuit is about 4365×605?m~2,and the area of the physical layer is about 4770×515?m~2.5.Build a test platform to conduct board-level tests on the ADC converter sample containing the transmitter to evaluate the actual performance of the transmitter.Provide 1 GHz input clock for the converter chip,and the converter performs 1 GSPS incoherent sampling on the 10.3 MHz sinusoidal signal generated by the signal source.The test results show that the converter has an signal-to-noise ratio(SNR)of 62.18 dB,signal-to-noise ratio(SINAD)of62.04 dBc,and spurious-free dynamic range(SFDR)of 74.12 dBc under this working condition.The test result shows that the sample function is normal,and the maximum data transmission rate of each channel is 12.5 Gbps.Compared with domestic related research,the link mode supported by this transmitter is richer and has advantages in data transmission rate.There are two main innovations in this paper:First,it proposes a three-level data mapping processing method at the transmission layer,which simplifies the mapping logic and can realize the sampling data framing function in multiple modes;second,it proposes a low latency By analyzing and summarizing the rules of the 8b/10b code table,the four-way parallel 8b/10b encoder has designed and realized the function module for rapid generation of polarity results.the encoder can correctly code the 32 bit data into 40 bit data in the next clock cycle,which can effectively reduce the encoding latency,improve the efficiency of the parallel coding.