Research And Design Of A New Advanced Successive Approximation ADC

Future technological development trends mainly include the Internet of Things(IoT),machine learning and artificial intelligence(AI),and so on.Over these years,with the development and advancement of CMOS technology,the ability of digital processing signals has made a huge leap.Its main manifestations are speed improvement,area reduction and power consumption reduction.However,as the interface between the analog domain and the digital domain,the analog-to-digital converter is still in the design bottleneck period.Traditional ADCs cannot improve accuracy through novel calibration methods.With the increase of integration complexity,typical applications put forward new requirements for the quantization capability of ADCs.Therefore,the ADC needs to continuously improve in the direction of high accuracy and low power consumption.The SAR ADC is one of the most energy-efficient analog-to-digital converters.This paper designs a SAR ADC based on charge redistribution and using SMIC 0.18?m MSBCD1.8V process.The main contributions of this article are as follows:1.The influence of unit capacitance mismatch on the linearity of high-precision ADCs is analyzed.Based on the theoretical knowledge of the normal distribution,a new calibration method based on the sorting and reconstruction of the capacitor array is designed.A system-level simulation was built on the MATLAB platform to verify the reliability of the method.The simulation results show that this method has a significant improvement in dynamic performance,which is conducive to further improvement of linearity,and there is no obvious additional power consumption.2.A capacitance comparison circuit suitable for differential capacitance digital-to-analog converter is proposed to compare the size of the capacitance;a novel digital bubble sorting circuit is designed which can be used to realize the capacitance follow-up Sort from big to small.Digital bubbling sorting circuit compared with the analog bubbling sorting circuit with switch array as the core in the past research,the complexity of the circuit is greatly reduced,and the sorting for N capacitors is realized,which can reduce the number of analog and digital connection signal lines from N~2 to N.The bubbling sorting circuit was built on the Cadence platform to verify the accuracy of the design.3.Designed a 14-bit 1 MS/s SAR ADC using the above-mentioned calibration method.The DAC adopts a hybrid architecture of a high 8-bit capacitor array and a low6-bit resistor array.Among them,the capacitor array adopts a binary weighted array of unit capacitors,and the resistor array adopts a voltage divider type.Choose to use the Vcm-based switching scheme to reduce the switching energy and area of the DAC.In order to obtain smaller power consumption and noise,a time domain comparator is used.Sampling is performed through the gate voltage bootstrap switch to reduce the non-linear error introduced when sampling the input signal.SAR logic control circuit realizes synchronous SAR control logic circuit in Verilog HDL language.The simulation results show that when the ADC works at a sampling rate of 1MS/s,the SFDR can be increased from 79.62 d B to 101.54 d B,and the SNDR can be increased from 75.92 d B(12.32 ENOB)to 84.39 d B(13.73 ENOB)based on the sequencing reconstruction calibration method.The factor(FOM)reaches 36.96 f J/conversion-step.