Research On A New Type Of Low-power FPGA Architecture

With the rapid development of Field Programmable Gate Array(FPGA),its applications in communication,control and other fields have become more and more extensive.The shrinking process size continues to promote the continuous increase of the number of FPGA logic gates,so the power management of the FPGA,especially the management of static power consumption,is at an important position in the development of low-power FPGAs in the future.At the same time,in the production process of FPGA devices with a large number of logic gates,due to the large chip area,the probability of defects is greater,which reduces the yield rate and increases the production cost.This paper applies gated power supply technology to the design of FPGA chips and proposes a new low-power FPGA structure.The main contents are as follows:(1)Based on the structure of a 20 million gate FPGA,four power switch network circuits are designed using overseas 40 nm process library,which are PMOS parallel switch chain,PMOS buffer parallel switch chain,soft start PMOS parallel switch chain and Soft start PMOS buffer parallel switch chain.The performance parameters such as voltage loss and driving ability of the above four power switch networks are compared and analyzed.The simulation results show that when the number of devices in parallel is greater than or equal to 400 and the channel width-to-length ratio is 30,better switching performance can be obtained.(2)Using Virtuoso software,a circuit model of two CLB logic blocks with power switch network and non-power switch network was established.The simulation results show that when the CLB logic block is in a static condition,compared with the CLB logic block without a power switch,the leakage power consumption of the CLB logic block with a power switch is reduced by 99.9897%.(3)In order to effectively improve the yield of FPGA chips,the paper proposes a new low-power FPGA structure based on anti-fuse device control,and designs anti-fuse device control circuits,including high-voltage programming circuits,oscillation circuits,and pumping circuits,Address decoding circuit and programming switch circuit.The simulation results show that this control circuit realizes the function of burning anti-fuse devices.(4)In order to reduce the static power consumption of FPGA chips,the paper proposes a new low-power FPGA structure based on PMC control.Firstly,the function description of PMC is realized by Verilog language.Then carry on the function simulation to it,the result shows that can realize the function of dynamic power management.Finally,through DC synthesis,the synthesis result shows that there is no timing violation in the front-end design of PMC.(5)The paper proposes a new low-power FPGA structure based on SRAM configuration point control.With this as the guiding idea,a CLB logic block circuit model is established in Virtuoso software.The simulation results show that SRAM can dynamically control the power switch network.Turn on and turn off,and the CLB logic block successfully implements the 128-bit shift register function.(6)In order to further verify the feasibility of low-power power gated FPGA devices,the paper designed a system-level low-power verification system based on Spartan-6 FPGA,and completed the design and testing of the PCB circuit board.The static test results show that the leakage power consumption of the FPGA chip when the power switch is turned off is more than 99.99% smaller than the leakage power consumption of the FPGA when the power switch is turned on.The dynamic test results show that the power switch and isolation unit settings in the low-power gated power supply FPGA device have no effect on the function realization and function configuration of the FPGA,and the application of gated power supply technology in the FPGA device has a high degree of achievability Sex.