Modeling Of Silicon-based Millimeter Wave Devices

With the production and use of large-scale integrated circuits and wireless communication technologies today,the electronic information industry has rapidly risen and become an important high-tech industry.Due to the explosive growth of demand in the electronics market,higher requirements have been placed on integrated circuits.CMOS technology not only has mature technology and high integration,but also has the advantages of low power consumption and low cost.Therefore,it stands out from the crowd and becomes the first choice for circuit design.With the rapid development of science and technology,the CMOS process node is constantly evolving in continuous research,making the size reduction of the device a reality,and the operating frequency of the device is also increasing.The model of the device is the basis for designing high-performance circuits,and the performance of the designed circuit can be predicted through an accurate model.Through accurate device characterization,the cycle of circuit design can be shortened and the success rate of the product can be improved.In today's electronic warfare where every second counts,accurate transistor models are extremely important.Therefore,this article has carried on the relevant modeling research based on 55 nm CMOS craft transistor.First of all,this article introduces the research background and significance of transistor modeling,classifies and introduces the development of MOSFET models,and investigates and analyzes relevant research trends at home and abroad.Secondly,the physical structure and working mechanism of the MOSFET device are introduced from the physical level,some typical physical effects represented in the model are analyzed,the basic knowledge of the BSIM4 model is summarized,and the development of CMOS process and the basic flow of modeling are briefly introduced.Subsequently,the size of the modeled device was determined and the modelling test layout was designed,and the on-chip test system and transistor test plan were briefly introduced.Since the mismatch between the device size and the test instrument will introduce the parasitic effects of the test structure,the small-signal S-parameters of the transistor are first de-embedded,and then the small-signal equivalent circuit model of the transistor is established,and based on the model-based topology,a corresponding multi-bias small-signal parameter extraction method is proposed.The model results are in good agreement with the test data,verifying the effectiveness of the parameter extraction method and the accuracy of the model.On this basis,a large-signal model based on the BSIM4 model was established by extrapolating the small-signal equivalent circuit model,and the nonlinear characteristics of the transistor were studied.According to the DC test results,the current parameters under the large signal were extracted,and the DC model was established.The S-parameter characterization under the large signal was verified,and the model parameters were extracted and optimized through the power sweep results under the optimal load impedance,and the large-signal model was established.Finally,the model was verified at the device level through load pulling.The results show that the model can accurately characterize the DC output characteristics of transistors and the output power,gain,power additional efficiency indicators.The model proposed in this article has high accuracy and has guiding significance for circuit design.