Optimal Design Of A Low-capacitance Transient Voltage Suppressor Protection Device

Electro-Static Discharge(ESD)is a very common natural phenomenon.Although static electricity hardly affects the human body,the ESD event may cause irreversible damage to electronic equipment and is one of the important reasons for the damage or failure of integrated circuit(IC)chips.In recent years,thanks to the upgrading of global semiconductor manufacturing technology,the characteristic dimension of ICs has been continuously reduced,making ICs more integrated,faster in calculations,and lower in power consumption,but at the same time,the chips are more and more sensitive to ESD events.In order to ensure the quality and reliability of electronic products,almost all chips require a certain level of ESD protection.In system design,with the increase of data transmission speed and signal frequency,the data interface has more and more stringent requirements for the parasitic capacitance of ESD protection devices,which also drives the development of the low-capacitance transient voltage suppressor(TVS),the parasitic capacitance of protection devices has also become an important research topic in ESDrelated fields.This thesis proposes a snapback low-capacitance TVS protection array and a nosnapback low-capacitance TVS protection array for common low-voltage data transmission interfaces.the snapback TVS device is based on the silicon-controlled rectifier(SCR)structure,which uses the strong ESD current capability of the SCR to reduce the required area of the device to reduce the parasitic capacitance,and at the same time uses the snapback characteristic to enhance the clamping capability of the device.Based on a simplified designed single-layer metal lateral manufacturing process,the TVS array with a low leakage current level is realized.The forward ESD current capability is as high as 90 m A/?m,and the parasitic capacitance level meets the requirements of the USB 3.2 Gen 1 standard interface.Corresponding improvement schemes are proposed for the shortcomings reflected in the test,and their effectiveness was verified through simulation and test respectively.The no-snapback low-capacitance TVS array is based on diode scheme,which uses guiding diodes to control the ESD current discharge direction and uses a zener diode as the core discharge device.Optimized on the basis of the original lateral process,the array has achieved a low leakage current level of the order of 10 n A,and can pass the ± 16 A TLP test.Finally,a TVS chip that is highly compatible with traditional processes and has excellent performance is obtained,which can simultaneously provide high-performance ESD protection for four high-speed signal pins and one direct-current(DC)power supply pin without the risk of latch-up.Common mode capacitance is as low as 0.35 p F and differential mode capacitance is less than 0.1 p F.Moreover,each pin of the chip has passed the IEC 61000-4-2 electrostatic standard ± 10 k V contact mode stress and the IEC61000-4-5 surge standard above 5 A stress,and the clamping performance is good.