Design Of 2*4 Array Ultra Low Capacitance ESD Protection Device

The phenomenon of electrostatic discharge(ESD)can happen randomly in the production,transportation and application of semiconductor chips.The occurrence of ESD events will generate great energy consumption,which will often have a destructive impact on the functions of chips and cause property losses.Therefore,qualified ESD protection devices are very important for chip and terminal manufacturers.With the development of 5G communication technology,data transmission speed may be greatly improved.ESD protection devices for high-speed data transmission interfaces require low capacitance to avoid data loss due to impedance mismatches.Based on this,this paper will design an ESD protection device mainly used for USB3.0 and HDMI data interface.The specific research contents are as follows:Firstly,this paper introduces the research background of the subject and the current research status in China and abroad,and explains the destructiveness of ESD and the importance of ESD protection to the IC industry.Then,starting from the principle of ESD protection,ESD protection devices are divided into snapback type and snapback type.Then the discharge model and test model of ESD are introduced respectively and the equivalent circuit and grade division of ESD protection under various models are given.Then,the protection principle of ESD protection devices commonly used such as diode,BJT and other system-level ESD protection devices like TVS are introduced,and their advantages and disadvantages are compared.Then the criterion of ESD failure is introduced.It indicates the direction for the subsequent structure,process design and simulation.After having certain theory foundation,the design goal of this design is put forward.Then the problem of over-triggering voltage in current design is pointed out and the solution of reducing triggering voltage by referring to auxiliary triggering devices is given.Then the process route is introduced and determined through the communication with foundry,and the key steps are explained and analyzed.Then the structure diagram of this design is given,and the capacitance of the device is reduced by series low capacitance diode.With the help of TCAD simulation software,the simulation is conducted on the basis of confirmed structure diagram,and the sequence of simulation is determined according to the complexity of device structure,so as to ensure that the simulation of each step will not affect the previous simulation results.Each set of simulation results will be explained theoretically and the optimal value by comparing the simulation results will be choosen.After all the device parameters meet the requirements,the devices are connected through the circuit and multi-pulse TLP simulation is conducted.Finally,the capacitance is 0.3pF,the trigger voltage is 6.86 V,the hold voltage is 1.5V,the forward clamping voltage is 5.7V under 8A,and the reverse clamping voltage is 3.5V.and the forward clamping voltage is 7.5V and reverse clamping voltage is 5.15 V at 16 A and the layout design scheme is given.At last,combined with foreign products,the design direction of ESD protection in the current market is proposed,which is of certain significance to the development of ESD array devices in the future.