Simulation Of The Performance And Failure Analysis On Ferroelectric Thin Film And Tunnel Junction Memory Devices

In this dissertation, we have mainly studied the application of thin films and tunnel junctions on ferroelectric memories. From the preparation of ferroelectric samples to the measurement of basic electric properties of thin films, and we also discussed the failure mechanism of ferroelectric thin films and devices in detail; investigated some theoretical model for polarization switching or failure mechanism; then discussed the physics of ferroelectric memory divices, fatigue failure of thin films and imprint of current-voltage loops of the transistor memory devices, the application of ultra thin ferroelectric or multiferroic films on new-type multilogic memory devices and so on. We have established the ferroelectric capacitance model, and used it to analyze the electrical properties of ferroelectric thin films and application-related failure of performance. We have established a ferroelectric capacitor model based on dipole switching and Preisach thoery, and used it to analyze the electrical properties of ferroelectric thin films and application-related failure of performance; we also proposed a new concept of multilogic memory devices, this type of device is expected to be one of ideal memory devices. Our work mainly focuses on the following six aspects:1. Thin films of Nd3+/V5+-cosubstituted bismuth titanate, i.e., (Bi4-xNdx) (Ti2.95V0.05)O12 (x=0,0.25 and 0.5), were fabricated by a chemical solution deposition technique. We have investigated the saturated and unsaturated hysteresis loop of the thin films with different Nd3+ contents. We found that excessive or insufficient Nd3+-content would decrease the remanent polarization. The frequency dependence of the remanent polarizations following a Curievon-Schweidler law satisfactorily was also investigated. The study enabled us deeply understood the bismuth titanate thin films with different Nd3+ contents.2. In the second section, a model has been developed for the P-E hysteresis behavior. It is based on the dipole switching theory and Preisach model that uses the DFIM approach. Hysteresis loops have been reproduced with the model to agree reasonably well with the experimental data measured from various ferroelectric thin films, such as BaTiO3 (BTO), Pb(Zr,,Ti1-x)O3 (PZT)-based, (Bax,Sr1-x)TiO3 (BST) and Bismuth Layer structured Ferroelectric (BLSF) thin films, have been simulated by our model. The model can also predict asymmetric hysteresis loop measured under unconventional situation. Additionally, the mathematical description can be easily combined with electronic design automation software in circuit simulation of ferroelectric capacitor or ferroelectric field effect transistor.3. Models for the electric displacement hysteresis and strain butterfly loops of ferroelectric films under electrical loading are proposed based on an improved Preisach model for nonlinear remanent polarization. Compared to the previous model, the current model, including the history-dependent electric field effect, which is always neglected in the conventional model, provides electric displacement and strain loops with a full and symmetric shape. The models show improved displacement and strain versus electric field loops that agree reasonably well with the experimental data. In addition, both the loops of electric displacement and strain under intrinsic defects and injected charges have also been investigated by our model.4. Incorporating the vacancy electromigration theory into the switching-induced charge-injection mechanism into the local phase decomposition model has led to an analytical model for the dielectric fatigue behavior and the remnant polarization in perovskite structured ferroelectric thin films. The model has allowed us to reproduce the fatigue behavior in various ferroelectric thin films measured under different voltages, temperatures, and frequencies. We concluded the essential reason for electrical fatigue in ferroelectrics is the local phase separation induced directly or indirectly by other fatigue mechanisms proposed in previous papers.5. Considering the thin nonswitching interface layer between the top electrode and ferroelectric thin film which is used as the gate dielectric, we introduce an improved device model, which is based on the physics of semiconductor devices, to describe the channel (or drain-source) current of the metal-ferroelectric-insulator field-effect transistor (MFIS-FET). In our model, the thickness ratio v of the nonswitching interface layer varies for different failure mechanisms or external applied electric voltage. Theoretical prediction based on this approach agree well with the recent experiments showed by Tabuchi et al. [Integrated Ferroelectrics 79,211 (2006)]. The results displayed the effect of interface layer thickness-ratio on the imprint of the channel current vs electric field loops. Finaly, we discussed the cause of imprint for both ferroelectric thin films and MFIS-FET devices.6. Based on the multiferroic tunnel junction, We firstly proposed the concept of octal data storage, and established a theoretical model, which is capable of producing the logic states by combining the spin-filter effect and the screening of polarization charges between two electrodes through a general spintronic tunneling. In order to make the octal data storage come true, we proposed two types of practical device structures combining a multiferroic tunnel junction with a magnetoelectric (ME) film in which the magnetic configuration is controlled by the electric field. Calculations embodying the Green's function approach show that the magnetic polarization can be switched on and off by an electric field in the ME film due to the effect of elastic coupling interaction. Using the spintronic tunneling model, we have produced eight logic states of tunnelling resistance in the tunnel junction and have obtained corresponding laws that control them. The dependence of the conductance ratio with very large magnitude on electric polarization, exchange splitting, barrier width, and bias voltage is investigated. The result may provide some insights into the realization of octal data storage (namely, the eight different logic states are used as octal code), which could lead to the tremendous increase of memory storage density.