A Low-power MCU Design Based On AMBA Bus Of Master Thesis

Since the 21 st century,with the rapid development of integrated circuits and the continuous shrinking of its foundry process nodes,our work and life have long been inseparable from integrated circuits.Emerging industries such as 5G,autonomous driving,industrial control,and the Internet of Things rely on integrated circuits,among which the Micro Control Unit(MCU)is one of the essential core modules.At present,most MCU products are designed for different application scenarios based on the CPU provided by ARM.The most common are 8-bit and 16-bit MCUs,which can basically meet the needs of the low-end market,but in the future,The 32-bit MCU with low power consumption and highly efficient will surely become the mainstream of the market.Based on the requirements of high performance and low power consumption,this article selects ARM's Cortex-M0 as the CPU,based on the AMBA bus protocol,combined with FPGA on-board debugging to complete the design,tapeout and verification of an 32-bit MCU chip.This article follows the design principle from top to down.First,it analyzes the internal structure of the Cortex-M0 core and the AMBA bus protocol,which provides theoretical support for subsequent MCU overall architecture design and specific design of each module.Then,the source of digital IC power consumption and the specific implementation method of low power consumption are explained,which provide a theoretical basis for the low-power design of each module.Based on the definition of MCU system functions and the division of modules,this paper completes the MCU architecture design,and the Verilog hardware language was written and simulated for each sub-module.In this process,a low-power design was implemented based on the theory of power optimization.After completing the design of each module,the top-level instantiation is written,and the source code design phase is completed.Then combined with Keil development tools and FPGA to realize the co-simulation of software and hardware,which greatly enhanced the reliability of the design.This article designs two versions of MCU.After the source code is written and simulated,the first version continues to complete DC synthesis,INNOVUS placement and routing,post-simulation,and layout output based on the CMOS 180 nm process.Design the PCB and build the test platform to complete the chip test,the clock frequency can run up to 80 MHz,and the logic output meets the basic expectations.On the basis of the first version,the second edition improved the MCU architecture and increased the core interrupt service module,which greatly reduced power consumption and enhanced the applicability of the MCU.Based on the CMOS 65 nm process,DC synthesis,INNOVUS placement and routing,post-simulation and FPGA verification have continued to be completed.The MCU is verified by the combination of software and hardware combined with FPGA.The clock frequency can run up to 100 MHz.When different external interrupts are given,the MCU can correctly respond to the interrupt and output the result correctly on the designated slave device,which is consistent with the simulation result.Meet the expected design.