Architectural enhancements for general-purpose processors and memory interfaces to improve performance for video applications

Decoding of a video bitstream, such as an MPEG-2 compliant video bitstream, requires high processor computation and imposes real-time decoding constraints. One of the major contributors to the total decoding time is the variable-length decoding process, which is serial in nature.; The first contribution of this thesis is the design of new hardware structures to speed up the variable-length decoding process. To investigate the potential performance gain of the proposed architectures, new instructions that use the proposed architectures are introduced into a general-purpose processor simulator to simulate the execution of code that processes standard MPEG-2 compliant bitstreams. The simulation includes pipeline stalls and cache miss penalties incurred in a general-purpose processor.; The second contribution of the thesis is the proposal of a new memory mapping technique for video pixels and the design of an associated interface architecture to support the memory mapping. The memory-interface architecture is implemented for a programmable logic device to verify the functionality and to quantify the hardware resource utilization.; The final contribution of this thesis is the development of a software tool for rapidly integrating low-level VHDL components through simple and easy-to-use declarations. (Abstract shortened by UMI.)...