Algorithm And Circuit Design Of Defected Pixel Correction For On-chip Image Sensor

As the number of cameras on mobile devices continues to increase,the market situation of CMOS image sensors has continued to be hot in recent years.Although the current image processing technology has been greatly improved,due to some objective reasons,there are always some defected pixels in the original pictures,which greatly affect the quality of images.Therefore,this paper will do some research on the problem of defected pixel correction of CMOS image sensor.Based on the characteristics of defected pixels in image sensor,to deal with the possible defected pixels in images,this paper adopts the method that carries out Static Defected Pixel Correction(SPC)and Dynamic Defected Pixel Correction(DPC)in order.Module SPC copes with the problem of 3×3 defected pixel cluster,and module DPC focuses on the problem of single defected pixel.In SPC,we compare with the static defected pixel table to detect the defected pixels and replace them by the mean value of related pixels.In DPC,we first expand the edge of the image.And then related pixels are used to detect the defected pixels.At last,the calculation of the direction gradient is introduced to correct dynamic defected pixels by mean value correction.Compared with the related defected pixel correction algorithm,the algorithm designed in this paper has the advantages of less calculation and better edge protection performance.It can also correct more types of defected pixel.This paper further optimizes the algorithm based on the system requirements in the process of hardware implementation.It adopts the pipeline operation with parallel modules,and reasonably allocates the resources on chip.This paper also carries out the system level verification of the two modules designed on UVM.As a result,it improves the efficiency of defected pixel correction and has good edge preserving property.Finally,HL55lp technology is used to synthesize the design in this paper.The design uses a total of 75.875 kb on-chip memory.Its highest clock frequency is up to 120MHz.The total power consumption is 233m W.And the total occupied area is 2.11mm~2.The chip products containing two modules designed in this project have realized the chip flow.