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The Design And Implementation Of Pixel Rate Offset And Shading Correction System For Scanner Based On Sopc

Posted on:2010-04-14Degree:MasterType:Thesis
Country:ChinaCandidate:D J ZhangFull Text:PDF
GTID:2198330332488640Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
SOPC (System On Programmable Chip) is a flexible and efficient solution for SOC.It is also an innvoting System design technology which relies on both software and hardware coordination. Embedded systems based on SOPC have advantages of small size, excellent performance, low power consumption, high reliability, and have been widely used in military, industrial control, consumable electronic products, network communication and many other fields. Nios II embedded processor is a CPU that is specially designed for SOPC and is provided to designer as IP core, while they can customize the required peripheral devices in the GUI of SOPC. As Nios II processors are configurable, they bring great flexibility into the design of embedded systems. In this paper, the design under SOPC for scanner controller and its pixel rate offset and shading correction will be discussed in detail.Because of offset errors generated by dark current and gain errors resulting from non-linear of CCD light-senitive device, the R, G, B three-channel image data of each pixel requires to be corrected.This paper focused on the design and application of pixel rate offset and shading correction system based on SOPC, while the main emphasis is on the design and realization of, pixel rate offset and shading correction of linear array CCD's analog front end.The introduction of this paper starts with the system developing platform, working characteristics of linear array CCD front-end processor LM98714 and the overall design of the pixel rate offset and shading correction system. Two designs of pixel rate offset and shading correction are discussed and completed subsequently, named software correction based on Nios II CPU and hardware logic correction based on cumstom peripherals IP core. Lastly, the design of external interfaces SPI and USB based on Nios II is decribed and the paper concludes with the integration and verification of the system.
Keywords/Search Tags:SOPC, IP core, Scanner, Pixel Rate Offset and Shading Correction SPI
PDF Full Text Request
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