Research And Design Of Carbon-based Monolithic 3D SRAM With High Integration Density And Yield

Static random access memory(SRAM)is an indispensable component on the chip which usually severs as the cache.However,the capacity of SRAM on the chip is increasing with the development of microprocessor,and the area occupied by SRAM is increasing.On the other hand,as the feature size of semiconductor devices continues to decrease,the yield of SRAM is decreased due to process variations,which seriously reduces the reliability of the chip.Therefore,improving the integration density and yield of SRAM is very important to reduce the area and improve the reliability of the chip.In recent years,carbon nanotube field-effect transistors(CN-MOSFETs)have become very promising semiconductor devices due to their extremely small physical size and energy delay product(EDP)benefit.On the other hand,due to the low temperature process of CN-MOSFETs,CN-MOSFET is naturally suitable for monolithic 3D(M3D)integration.The previously published 6-CN-MOSFET and 8-CN-MOSFET SRAM cells suffer from huge inter-layer area skew under M3 D integration,resulting in a decrease in integration density.On the other hand,metallic carbon nanotubes in every device layer in M3 D CN-MOSFET integrated circuits will seriously reduce the yield of the circuit.In view of these two issues,the main research contents and results of this paper are as follows:1.By considering the spatial correlation of each CN-MOSFET in M3 D integrated circuits and the statistical probability of metallic carbon nanotubes,we proposed a functional yield model suitable for M3 D CN-MOSFET circuits.Based on this functional yield model,we proposed a design method for high-yield M3 D CN-MOSFET SRAM with metallic carbon nanotube tolerance.The functional yields of the proposed 16K-bit arrays of M3 D 3N3P,4N4P-PRD and 4N4P-PAX SRAM reached 97.92%,96.87% and 96.87%,respectively.The results of 1000 Monte-Carlo simulations show the tolerance of metallic CN removal technology in the porposed SRAM circuits.2.By balancing the number and sizing of n-channel and p-channel CN-MOSFETs in the SRAM cell,the integration densities of the 16K-bit array of M3 D 3N3P,4N4P-PRD and 4N4P-PAX SRAM is increased by38.24%,46.11%,and 46.11%,respectively,as compared with the conventional M3 D SRAM arrays.Futhermore,as compared to the M3D6-CN-MOSFET and 8-CN-MOSFET SRAM arrays,the integration densith is increased by 1.58% and 38.24%,respectively.Hspice simulation shows that the M3 D 4N4P-PRD and 4N4P-PAX SRAM cells designed in this paper have 2.03 x read static noise margin and 8.91% higher write voltage margin as compared to the traditional 6T SRAM cell.