Improved Electrical Performances Of MoS₂ Field-effect Transistor With High-k Gate Dielectric

The characteristic length of silicon-based CMOS technology has been scaled to 10-nm technology node nowadays,while more critical short channel effect(SCE)limits its continuing scaling down.As an emerging 2-dimentional(2D)material,MoS2 has many advantages like natural 2D layered structure,easily to be thinned to nm-level thickness,free of dangling bonds,relative wide bandgap and tiny SCE,which make it a promising candidate for replace silicon in semiconductor industry.Due to the lack of work in improving interface quality of MoS2 transistors and effective screening to the Coulombic impurities(CI)screening,the reported mobility in experiments is smaller than the theoretical limit.Also,the widely used micromechanical exfoliation method and electron beam lithography(EBL)can't satisfy the mass production of future semiconductor industry.Aiming at solving the above two problems in this thesis,methods to improve the high-k gate dielectric/MoS2 interfacial quality and the screening effect to CI scattering together with processes applicable to future industry are studied.A comprehensive CI scattering limited mobility model considering both high-k dielectric screening effect and channel electron screening effect is built,and the influence of k value and transistor configuration on CI scattering limited mobility is discussed.Experimentally,atomic layer deposited(ALD)HfO2 back gate dielectric is annealed in different temperatures(400 ? and 500 ?)and different ambients(N2,O2 and NH3)before multilayer MoS2 transsitors' fabrication.By investigating the influence of annealing conditions on interfacial quality and electrical performance of the transistors,the optimum condition is 400 ?/NH3,which gives rise to improvement from 3.02×1012 eV-1 cm-2 to 5.73×1012eV-1cm-2 and improvement from 5.54 cm2/V·s to 15.1 cm2/V·s compared with transistors without annealing for the density of interfacial traps(Dit)performance and mobility performance respectively.An enlarged k value of gate dielectric HfTiO is achieved by alternately ALD HfO2 cycles and TiO2 cycles,the annealing of NH3 ambient at 400 ? also has the maximuim improvement on electrical performances of fabricated transistors compared with other annealing ambients,which means NH3 annealing ambient has the most passivation effect on defects and traps of high-k and high-k/MoS2 interface.On the basis of the above experiment investigations,HfO2 back gate dielectric prepared by ALD at 95 ? is annealed in NH3 ambient at 400 ? before fabricating few-layered MoS2 transistors.The mobility of transistors is greatly improved from 19.1 cm2/V·s to 42.1 cm2/V·s after deposition Y2O3/HfO2 encapsulation layer and so are other electrical characteristics,which indicates a high-k dielectric fully encapsulated MoS2 transistor configuration has stronger screening effect on Coulombic impurities scattering than high-k dielectric back-gated trsnsistors without encapsulation layer.At last,top-gated 6-layer-MoS2 transistors are made by conventional semiconductor processes like thermal chemical vapor deposition(CVD)for continuous and uniform MoS2 film and mask lithography for patterning of electrodes.The buffer layer of CVD MoS2 transistor is optimized,and Ta2O5 is found to be better than Al2O3 with higher mobility of 0.69 cm2/V s.Theoretically,a dielectric/MoS2/dielectric stacked layer model is established,and the analytical solution of the electrical potential field is obtained by solving the Possion equtions using image charge method.The k values of dielectrics used in the numerical calculation are extracted from experimental results,which are 20 and 12.86 for the ALD HfO2 of different deposition temperatures of 250 ? and 95 ? respectively.A dielectric screening function ?_k(q)is defined as the relative strength of electrical potential after Fourier transform,and a generalized screening function se(q)is defined to characterize the strength of screening effect originating from MoS2 channel electrons.The Coulombic impurities limited mobility is derived from Fermi's golden rule,with screening effects of both dielectric and channel electrons considered.The calculation results indicate that MoS2 transistors with dielectric of higher k values,high-k capsulation layer and higher channel electron density have higher mobility,which is in accordance with experimental results and provide potential strategies for designing MoS2 transistors with high electrical performance.